[PATCH] target/hppa: Set FPCR exception flag bits for non-trapped exceptions

[PATCH] target/hppa: Set FPCR exception flag bits for non-trapped exceptions

[Peter Maydell]

In commit ebd394948de4e8 ("target/hppa: Fix FPE exceptions") when
we added the code for setting up the registers correctly on trapping
FP exceptions, we accidentally broke the handling of the flag bits
for non-trapping exceptions.

In update_fr0_op() we incorrectly zero out the flag bits and the C
bit, so any fp operation would clear previously set flag bits. We
also stopped setting the flag bits when the fp operation raises
an exception and the trap is not enabled.

Adjust the code so that we set the Flag bits for every exception that
happened and where the trap is not enabled.  (This is the correct
behaviour for the case where an instruction triggers two exceptions,
one of which traps and one of which does not; that can only happen
for inexact + underflow or inexact + overflow.)

Cc: qemu-stable@nongnu.org
Fixes: ebd394948de4e8 ("target/hppa: Fix FPE exceptions")
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/3158
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/hppa/fpu_helper.c | 7 ++++++-
 1 file changed, 6 insertions(+), 1 deletion(-)

diff --git a/target/hppa/fpu_helper.c b/target/hppa/fpu_helper.c
index 45353202fae..2d272730f60 100644
--- a/target/hppa/fpu_helper.c
+++ b/target/hppa/fpu_helper.c
@@ -94,7 +94,8 @@ static void update_fr0_op(CPUHPPAState *env, uintptr_t ra)
 {
     uint32_t soft_exp = get_float_exception_flags(&env->fp_status);
     uint32_t hard_exp = 0;
-    uint32_t shadow = env->fr0_shadow & 0x3ffffff;
+    uint32_t shadow = env->fr0_shadow;
+    uint32_t to_flag = 0;
     uint32_t fr1 = 0;
 
     if (likely(soft_exp == 0)) {
@@ -122,6 +123,10 @@ static void update_fr0_op(CPUHPPAState *env, uintptr_t ra)
             fr1 |= hard_exp << (R_FPSR_FLAGS_SHIFT - R_FPSR_ENABLES_SHIFT);
         }
     }
+    /* Set the Flag bits for every exception that was not enabled */
+    to_flag = hard_exp & ~shadow;
+    shadow |= to_flag << (R_FPSR_FLAGS_SHIFT - R_FPSR_ENABLES_SHIFT);
+
     env->fr0_shadow = shadow;
     env->fr[0] = (uint64_t)shadow << 32 | fr1;
 
-- 
2.43.0

Re: [PATCH] target/hppa: Set FPCR exception flag bits for non-trapped exceptions

[Philippe Mathieu-Daudé]

Cc'ing Gabriel

On 17/10/25 10:53, Peter Maydell wrote:
> In commit ebd394948de4e8 ("target/hppa: Fix FPE exceptions") when
> we added the code for setting up the registers correctly on trapping
> FP exceptions, we accidentally broke the handling of the flag bits
> for non-trapping exceptions.
> 
> In update_fr0_op() we incorrectly zero out the flag bits and the C
> bit, so any fp operation would clear previously set flag bits. We
> also stopped setting the flag bits when the fp operation raises
> an exception and the trap is not enabled.
> 
> Adjust the code so that we set the Flag bits for every exception that
> happened and where the trap is not enabled.  (This is the correct
> behaviour for the case where an instruction triggers two exceptions,
> one of which traps and one of which does not; that can only happen
> for inexact + underflow or inexact + overflow.)
> 
> Cc: qemu-stable@nongnu.org
> Fixes: ebd394948de4e8 ("target/hppa: Fix FPE exceptions")
> Resolves: https://gitlab.com/qemu-project/qemu/-/issues/3158
> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
> ---
>   target/hppa/fpu_helper.c | 7 ++++++-
>   1 file changed, 6 insertions(+), 1 deletion(-)
> 
> diff --git a/target/hppa/fpu_helper.c b/target/hppa/fpu_helper.c
> index 45353202fae..2d272730f60 100644
> --- a/target/hppa/fpu_helper.c
> +++ b/target/hppa/fpu_helper.c
> @@ -94,7 +94,8 @@ static void update_fr0_op(CPUHPPAState *env, uintptr_t ra)
>   {
>       uint32_t soft_exp = get_float_exception_flags(&env->fp_status);
>       uint32_t hard_exp = 0;
> -    uint32_t shadow = env->fr0_shadow & 0x3ffffff;
> +    uint32_t shadow = env->fr0_shadow;
> +    uint32_t to_flag = 0;
>       uint32_t fr1 = 0;
>   
>       if (likely(soft_exp == 0)) {
> @@ -122,6 +123,10 @@ static void update_fr0_op(CPUHPPAState *env, uintptr_t ra)
>               fr1 |= hard_exp << (R_FPSR_FLAGS_SHIFT - R_FPSR_ENABLES_SHIFT);
>           }
>       }
> +    /* Set the Flag bits for every exception that was not enabled */
> +    to_flag = hard_exp & ~shadow;
> +    shadow |= to_flag << (R_FPSR_FLAGS_SHIFT - R_FPSR_ENABLES_SHIFT);
> +
>       env->fr0_shadow = shadow;
>       env->fr[0] = (uint64_t)shadow << 32 | fr1;
>   

Re: [PATCH] target/hppa: Set FPCR exception flag bits for non-trapped exceptions

[Helge Deller]

On 10/22/25 21:00, Philippe Mathieu-Daudé wrote:
> On 17/10/25 10:53, Peter Maydell wrote:
>> In commit ebd394948de4e8 ("target/hppa: Fix FPE exceptions") when
>> we added the code for setting up the registers correctly on trapping
>> FP exceptions, we accidentally broke the handling of the flag bits
>> for non-trapping exceptions.
>>
>> In update_fr0_op() we incorrectly zero out the flag bits and the C
>> bit, so any fp operation would clear previously set flag bits. We
>> also stopped setting the flag bits when the fp operation raises
>> an exception and the trap is not enabled.
>>
>> Adjust the code so that we set the Flag bits for every exception that
>> happened and where the trap is not enabled.  (This is the correct
>> behaviour for the case where an instruction triggers two exceptions,
>> one of which traps and one of which does not; that can only happen
>> for inexact + underflow or inexact + overflow.)
>>
>> Cc: qemu-stable@nongnu.org
>> Fixes: ebd394948de4e8 ("target/hppa: Fix FPE exceptions")
>> Resolves: 
>> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

Reviewed-by: Helge Deller <deller@gmx.de>
Tested-by: Helge Deller <deller@gmx.de>

Thanks!
Helge

>> ---
>>   target/hppa/fpu_helper.c | 7 ++++++-
>>   1 file changed, 6 insertions(+), 1 deletion(-)
>>
>> diff --git a/target/hppa/fpu_helper.c b/target/hppa/fpu_helper.c
>> index 45353202fae..2d272730f60 100644
>> --- a/target/hppa/fpu_helper.c
>> +++ b/target/hppa/fpu_helper.c
>> @@ -94,7 +94,8 @@ static void update_fr0_op(CPUHPPAState *env, uintptr_t ra)
>>   {
>>       uint32_t soft_exp = get_float_exception_flags(&env->fp_status);
>>       uint32_t hard_exp = 0;
>> -    uint32_t shadow = env->fr0_shadow & 0x3ffffff;
>> +    uint32_t shadow = env->fr0_shadow;
>> +    uint32_t to_flag = 0;
>>       uint32_t fr1 = 0;
>>       if (likely(soft_exp == 0)) {
>> @@ -122,6 +123,10 @@ static void update_fr0_op(CPUHPPAState *env, uintptr_t ra)
>>               fr1 |= hard_exp << (R_FPSR_FLAGS_SHIFT - R_FPSR_ENABLES_SHIFT);
>>           }
>>       }
>> +    /* Set the Flag bits for every exception that was not enabled */
>> +    to_flag = hard_exp & ~shadow;
>> +    shadow |= to_flag << (R_FPSR_FLAGS_SHIFT - R_FPSR_ENABLES_SHIFT);
>> +
>>       env->fr0_shadow = shadow;
>>       env->fr[0] = (uint64_t)shadow << 32 | fr1;
> 

Re: [PATCH] target/hppa: Set FPCR exception flag bits for non-trapped exceptions

[Philippe Mathieu-Daudé]

On 17/10/25 10:53, Peter Maydell wrote:
> In commit ebd394948de4e8 ("target/hppa: Fix FPE exceptions") when
> we added the code for setting up the registers correctly on trapping
> FP exceptions, we accidentally broke the handling of the flag bits
> for non-trapping exceptions.
> 
> In update_fr0_op() we incorrectly zero out the flag bits and the C
> bit, so any fp operation would clear previously set flag bits. We
> also stopped setting the flag bits when the fp operation raises
> an exception and the trap is not enabled.
> 
> Adjust the code so that we set the Flag bits for every exception that
> happened and where the trap is not enabled.  (This is the correct
> behaviour for the case where an instruction triggers two exceptions,
> one of which traps and one of which does not; that can only happen
> for inexact + underflow or inexact + overflow.)
> 
> Cc: qemu-stable@nongnu.org
> Fixes: ebd394948de4e8 ("target/hppa: Fix FPE exceptions")
> Resolves: https://gitlab.com/qemu-project/qemu/-/issues/3158
> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
> ---
>   target/hppa/fpu_helper.c | 7 ++++++-
>   1 file changed, 6 insertions(+), 1 deletion(-)

Queued via hw-misc, thanks!