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[88.21.68.240]) by smtp.gmail.com with ESMTPSA id q192sm5084554wme.23.2019.09.21.02.09.40 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Sat, 21 Sep 2019 02:09:43 -0700 (PDT) Subject: Re: [Qemu-devel] [PATCH v1 1/2] RISC-V: Handle bus errors in the page table walker To: Alistair Francis , qemu-devel@nongnu.org, qemu-riscv@nongnu.org References: From: =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= Openpgp: id=89C1E78F601EE86C867495CBA2A3FD6EDEADC0DE; url=http://pgp.mit.edu/pks/lookup?op=get&search=0xA2A3FD6EDEADC0DE Message-ID: Date: Sat, 21 Sep 2019 11:09:40 +0200 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:60.0) Gecko/20100101 Thunderbird/60.7.0 MIME-Version: 1.0 In-Reply-To: Content-Language: en-US X-MC-Unique: dEtHa5OpMVm5qU7OEqfnjw-1 X-Mimecast-Spam-Score: 0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 207.211.31.120 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, palmer@sifive.com, alistair23@gmail.com Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On 9/18/19 1:22 AM, Alistair Francis wrote: > From: Palmer Dabbelt >=20 > We directly access physical memory while walking the page tables on > RISC-V, but while doing so we were using cpu_ld*() which does not report > bus errors. This patch converts the page table walker over to use > address_space_ld*(), which allows bus errors to be detected. >=20 > Signed-off-by: Palmer Dabbelt > Signed-off-by: Alistair Francis > --- > target/riscv/cpu_helper.c | 12 +++++++++--- > 1 file changed, 9 insertions(+), 3 deletions(-) >=20 > diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c > index 87dd6a6ece..c82e7ed52b 100644 > --- a/target/riscv/cpu_helper.c > +++ b/target/riscv/cpu_helper.c > @@ -169,7 +169,8 @@ static int get_physical_address(CPURISCVState *env, h= waddr *physical, > /* NOTE: the env->pc value visible here will not be > * correct, but the value visible to the exception handler > * (riscv_cpu_do_interrupt) is correct */ > - > + MemTxResult res; > + MemTxAttrs attrs =3D MEMTXATTRS_UNSPECIFIED; > int mode =3D mmu_idx; > =20 > if (mode =3D=3D PRV_M && access_type !=3D MMU_INST_FETCH) { > @@ -256,11 +257,16 @@ restart: > 1 << MMU_DATA_LOAD, PRV_S)) { > return TRANSLATE_PMP_FAIL; > } > + > #if defined(TARGET_RISCV32) > - target_ulong pte =3D ldl_phys(cs->as, pte_addr); > + target_ulong pte =3D address_space_ldl(cs->as, pte_addr, attrs, = &res); > #elif defined(TARGET_RISCV64) > - target_ulong pte =3D ldq_phys(cs->as, pte_addr); > + target_ulong pte =3D address_space_ldq(cs->as, pte_addr, attrs, = &res); > #endif > + if (res !=3D MEMTX_OK) { > + return TRANSLATE_FAIL; > + } > + > hwaddr ppn =3D pte >> PTE_PPN_SHIFT; > =20 > if (!(pte & PTE_V)) { >=20 Reviewed-by: Philippe Mathieu-Daud=C3=A9