From: Michael Tokarev <mjt@tls.msk.ru>
To: Deepak Gupta <debug@rivosinc.com>,
qemu-riscv@nongnu.org, qemu-devel@nongnu.org
Cc: palmer@dabbelt.com, alistair.francis@wdc.com, bmeng.cn@gmail.com,
liwei1518@gmail.com, dbarboza@ventanamicro.com,
zhiwei_liu@linux.alibaba.com,
Adam Zabrocki <azabrocki@nvidia.com>
Subject: Re: [PATCH v2 1/2] target/riscv: fix access permission checks for CSR_SSP
Date: Fri, 21 Mar 2025 21:01:57 +0300 [thread overview]
Message-ID: <b47fd8e8-f0dd-448f-ac9f-f6e23aead1bb@tls.msk.ru> (raw)
In-Reply-To: <20250306064636.452396-1-debug@rivosinc.com>
On 06.03.2025 09:46, Deepak Gupta wrote:
> Commit:8205bc1 ("target/riscv: introduce ssp and enabling controls for
> zicfiss") introduced CSR_SSP but it mis-interpreted the spec on access
> to CSR_SSP in M-mode. Gated to CSR_SSP is not gated via `xSSE`. But
> rather rules clearly specified in section "22.2.1. Shadow Stack Pointer
> (ssp) CSR access contr" in the priv spec.
>
> Fixes: 8205bc127a83 ("target/riscv: introduce ssp and enabling controls
> for zicfiss". Thanks to Adam Zabrocki for bringing this to attention.
Is this patchset (including "[2/2] target/riscv: fixes a bug against
`ssamoswap` behavior in M-mode") applicable for stable qemu series?
Thanks,
/mjt
next prev parent reply other threads:[~2025-03-21 18:02 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-03-06 6:46 [PATCH v2 1/2] target/riscv: fix access permission checks for CSR_SSP Deepak Gupta
2025-03-06 6:46 ` [PATCH v2 2/2] target/riscv: fixes a bug against `ssamoswap` behavior in M-mode Deepak Gupta
2025-03-07 1:59 ` Alistair Francis
2025-03-07 2:04 ` Alistair Francis
2025-03-07 3:23 ` Deepak Gupta
2025-03-21 18:01 ` Michael Tokarev [this message]
2025-03-24 3:05 ` [PATCH v2 1/2] target/riscv: fix access permission checks for CSR_SSP Alistair Francis
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