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[24.113.166.229]) by smtp.gmail.com with ESMTPSA id fa22-20020a17090af0d600b0023d1976cd34sm8619931pjb.17.2023.03.21.20.31.27 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 21 Mar 2023 20:31:28 -0700 (PDT) Message-ID: Date: Tue, 21 Mar 2023 20:31:25 -0700 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.8.0 Subject: Re: [PATCH] target/riscv: reduce overhead of MSTATUS_SUM change To: "Wu, Fei" , LIU Zhiwei Cc: Palmer Dabbelt , Alistair Francis , Bin Meng , Weiwei Li , Daniel Henrique Barboza , "open list:RISC-V TCG CPUs" , "open list:All patches CC here" References: <20230321063746.151107-1-fei2.wu@intel.com> <609e4659-532f-0fe2-447a-f7deaa0824e5@linaro.org> <209d36a3-c136-5288-a842-3c0b5f1b5d0a@linux.alibaba.com> <4f63f756-55d1-70f6-10e1-875c1e515fdf@intel.com> Content-Language: en-US From: Richard Henderson In-Reply-To: <4f63f756-55d1-70f6-10e1-875c1e515fdf@intel.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::633; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x633.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, NICE_REPLY_A=-0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On 3/21/23 19:47, Wu, Fei wrote: >>> You should be making use of different softmmu indexes, similar to how >>> ARM uses a separate index for PAN (privileged access never) mode.  If >>> I read the manual properly, PAN == !SUM. >>> >>> When you do this, you need no additional flushing. >> >> Hi Fei, >> >> Let's follow Richard's advice. >> Yes, I'm thinking about how to do it, and thank Richard for the advice. > > My question is: > * If we ensure this separate index (S+SUM) has no overlapping tlb > entries with S-mode (ignore M-mode so far), during SUM=1, we have to > look into both (S+SUM) and S index for kernel address translation, that > should be not desired. This is an incorrect assumption. S+SUM may very well have overlapping tlb entries with S. With SUM=1, you *only* look in S+SUM index; with SUM=0, you *only* look in S index. The only difference is a check in get_physical_address is no longer against MSTATUS_SUM directly, but against the mmu_index. > * If all the tlb operations are against (S+SUM) during SUM=1, then > (S+SUM) could contain some duplicated tlb entries of kernel address in S > index, the duplication means extra tlb lookup and fill. Yes, if the same address is probed via S and S+SUM, there is a duplicated lookup. But this is harmless. > Also if we want > to flush tlb entry of specific addr0, we have to flush both index. Yes, this is also true. But so far target/riscv is making no use of per-mmuidx flushing. At the moment you're *only* using tlb_flush(cpu), which flushes every mmuidx. Nor are you making use of per-page flushing. So, really, no change required at all there. r~