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([2602:47:d49d:ec01:986f:cb56:6709:4057]) by smtp.gmail.com with ESMTPSA id cp16-20020a170902e79000b0017834a6966csm3523509plb.176.2022.09.28.05.15.27 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 28 Sep 2022 05:15:27 -0700 (PDT) Message-ID: Date: Wed, 28 Sep 2022 05:15:25 -0700 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:91.0) Gecko/20100101 Thunderbird/91.11.0 Subject: Re: [PATCH 2/3] target/arm: Make writes to MDCR_EL3 use PMU start/finish calls Content-Language: en-US To: Peter Maydell , qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Thomas Huth References: <20220923123412.1214041-1-peter.maydell@linaro.org> <20220923123412.1214041-3-peter.maydell@linaro.org> From: Richard Henderson In-Reply-To: <20220923123412.1214041-3-peter.maydell@linaro.org> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=2607:f8b0:4864:20::431; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x431.google.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, NICE_REPLY_A=-2.319, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On 9/23/22 05:34, Peter Maydell wrote: > In commit 01765386a88868 we fixed a bug where we weren't correctly > bracketing changes to some registers with pmu_op_start() and > pmu_op_finish() calls for changes which affect whether the PMU > counters might be enabled. However, we missed the case of writes to > the AArch64 MDCR_EL3 register, because (unlike its AArch32 > counterpart) they are currently done directly to the CPU state struct > without going through the sdcr_write() function. > > Give MDCR_EL3 a writefn which handles the PMU start/finish calls. > The SDCR writefn then simplfies to "call the MDCR_EL3 writefn after > masking off the bits which don't exist in the AArch32 register". > > Signed-off-by: Peter Maydell > --- > target/arm/helper.c | 18 ++++++++++++++---- > 1 file changed, 14 insertions(+), 4 deletions(-) Reviewed-by: Richard Henderson r~