From: "Philippe Mathieu-Daudé" <philmd@linaro.org>
To: Jonathan Cameron <Jonathan.Cameron@huawei.com>,
qemu-devel@nongnu.org, Michael Tsirkin <mst@redhat.com>,
Fan Ni <fan.ni@samsung.com>,
linux-cxl@vger.kernel.org
Cc: linuxarm@huawei.com
Subject: Re: [PATCH v3 3/4] hw/cxl: Fix and use same calculation for HDM decoder block size everywhere
Date: Wed, 13 Sep 2023 08:53:55 +0200 [thread overview]
Message-ID: <b4ad0199-2df5-05ee-dde4-eb85ffb0a2b0@linaro.org> (raw)
In-Reply-To: <20230911114313.6144-4-Jonathan.Cameron@huawei.com>
On 11/9/23 13:43, Jonathan Cameron wrote:
> In order to avoid having the size of the per HDM decoder register block
> repeated in lots of places, create the register definitions for HDM
> decoder 1 and use the offset between the first registers in HDM decoder 0 and
> HDM decoder 1 to establish the offset.
>
> Calculate in each function as this is more obvious and leads to shorter
> line lengths than a single #define which would need a long name
> to be specific enough.
>
> Note that the code currently only supports one decoder, so the bugs this
> fixes don't actually affect anything. Previously the offset didn't
> take into account that the write_msk etc are 4 byte fields.
>
> Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
>
> --
> v3:
> New patch to separate this out from the addition of HDM decoders.
> ---
> include/hw/cxl/cxl_component.h | 2 ++
> hw/cxl/cxl-component-utils.c | 19 +++++++++++--------
> hw/cxl/cxl-host.c | 4 +++-
> hw/mem/cxl_type3.c | 24 +++++++++++++++---------
> 4 files changed, 31 insertions(+), 18 deletions(-)
> @@ -761,26 +763,30 @@ static void ct3_exit(PCIDevice *pci_dev)
> /* TODO: Support multiple HDM decoders and DPA skip */
> static bool cxl_type3_dpa(CXLType3Dev *ct3d, hwaddr host_addr, uint64_t *dpa)
> {
> + int hdm_inc = R_CXL_HDM_DECODER1_BASE_LO - R_CXL_HDM_DECODER0_BASE_LO;
> uint32_t *cache_mem = ct3d->cxl_cstate.crb.cache_mem_registers;
> uint64_t decoder_base, decoder_size, hpa_offset;
> uint32_t hdm0_ctrl;
> int ig, iw;
> + int i = 0;
>
> - decoder_base = (((uint64_t)cache_mem[R_CXL_HDM_DECODER0_BASE_HI] << 32) |
> - cache_mem[R_CXL_HDM_DECODER0_BASE_LO]);
> + decoder_base =
> + (((uint64_t)cache_mem[R_CXL_HDM_DECODER0_BASE_HI + i * hdm_inc] << 32) |
> + cache_mem[R_CXL_HDM_DECODER0_BASE_LO + i * hdm_inc]);
Alternatively easier to review as (matter of taste ?):
decoder_base = deposit64(cache_mem[R_CXL_HDM_DECODER0_BASE_LO + i *
hdm_inc], 32, 32,
cache_mem[R_CXL_HDM_DECODER0_BASE_HI + i *
hdm_inc]);
Regardless:
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
next prev parent reply other threads:[~2023-09-13 6:55 UTC|newest]
Thread overview: 13+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-09-11 11:43 [PATCH v3 0/4] hw/cxl: Support emulating 4 HDM decoders throughout topology Jonathan Cameron via
2023-09-11 11:43 ` [PATCH v3 1/4] hw/cxl: Push cxl_decoder_count_enc() and cxl_decode_ig() into .c Jonathan Cameron via
[not found] ` <CGME20230912161441uscas1p11618b32cdd50462c8267f12e1518e590@uscas1p1.samsung.com>
2023-09-12 16:14 ` Fan Ni
2023-09-11 11:43 ` [PATCH v3 2/4] hw/cxl: Add utility functions decoder interleave ways and target count Jonathan Cameron via
[not found] ` <CGME20230912172006uscas1p1f48a880aeaf7fad3400929d4bc919ae5@uscas1p1.samsung.com>
2023-09-12 17:20 ` Fan Ni
2023-09-13 8:58 ` Jonathan Cameron via
2023-09-11 11:43 ` [PATCH v3 3/4] hw/cxl: Fix and use same calculation for HDM decoder block size everywhere Jonathan Cameron via
[not found] ` <CGME20230912174357uscas1p23b767b0b88830d2b8a7179439d224a9e@uscas1p2.samsung.com>
2023-09-12 17:43 ` Fan Ni
2023-09-13 6:53 ` Philippe Mathieu-Daudé [this message]
2023-09-13 9:01 ` Jonathan Cameron via
2023-09-11 11:43 ` [PATCH v3 4/4] hw/cxl: Support 4 HDM decoders at all levels of topology Jonathan Cameron via
[not found] ` <CGME20230912180845uscas1p28e989eaff6b92939cfdb85886137354b@uscas1p2.samsung.com>
2023-09-12 18:08 ` Fan Ni
2023-09-13 9:03 ` Jonathan Cameron via
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