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[176.131.211.241]) by smtp.gmail.com with ESMTPSA id l21-20020a170906939500b00985ed2f1584sm7845653ejx.187.2023.09.12.23.53.56 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 12 Sep 2023 23:53:57 -0700 (PDT) Message-ID: Date: Wed, 13 Sep 2023 08:53:55 +0200 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Macintosh; Intel Mac OS X 10.15; rv:102.0) Gecko/20100101 Thunderbird/102.15.0 Subject: Re: [PATCH v3 3/4] hw/cxl: Fix and use same calculation for HDM decoder block size everywhere Content-Language: en-US To: Jonathan Cameron , qemu-devel@nongnu.org, Michael Tsirkin , Fan Ni , linux-cxl@vger.kernel.org Cc: linuxarm@huawei.com References: <20230911114313.6144-1-Jonathan.Cameron@huawei.com> <20230911114313.6144-4-Jonathan.Cameron@huawei.com> From: =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= In-Reply-To: <20230911114313.6144-4-Jonathan.Cameron@huawei.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::22a; envelope-from=philmd@linaro.org; helo=mail-lj1-x22a.google.com X-Spam_score_int: -35 X-Spam_score: -3.6 X-Spam_bar: --- X-Spam_report: (-3.6 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, NICE_REPLY_A=-1.473, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On 11/9/23 13:43, Jonathan Cameron wrote: > In order to avoid having the size of the per HDM decoder register block > repeated in lots of places, create the register definitions for HDM > decoder 1 and use the offset between the first registers in HDM decoder 0 and > HDM decoder 1 to establish the offset. > > Calculate in each function as this is more obvious and leads to shorter > line lengths than a single #define which would need a long name > to be specific enough. > > Note that the code currently only supports one decoder, so the bugs this > fixes don't actually affect anything. Previously the offset didn't > take into account that the write_msk etc are 4 byte fields. > > Signed-off-by: Jonathan Cameron > > -- > v3: > New patch to separate this out from the addition of HDM decoders. > --- > include/hw/cxl/cxl_component.h | 2 ++ > hw/cxl/cxl-component-utils.c | 19 +++++++++++-------- > hw/cxl/cxl-host.c | 4 +++- > hw/mem/cxl_type3.c | 24 +++++++++++++++--------- > 4 files changed, 31 insertions(+), 18 deletions(-) > @@ -761,26 +763,30 @@ static void ct3_exit(PCIDevice *pci_dev) > /* TODO: Support multiple HDM decoders and DPA skip */ > static bool cxl_type3_dpa(CXLType3Dev *ct3d, hwaddr host_addr, uint64_t *dpa) > { > + int hdm_inc = R_CXL_HDM_DECODER1_BASE_LO - R_CXL_HDM_DECODER0_BASE_LO; > uint32_t *cache_mem = ct3d->cxl_cstate.crb.cache_mem_registers; > uint64_t decoder_base, decoder_size, hpa_offset; > uint32_t hdm0_ctrl; > int ig, iw; > + int i = 0; > > - decoder_base = (((uint64_t)cache_mem[R_CXL_HDM_DECODER0_BASE_HI] << 32) | > - cache_mem[R_CXL_HDM_DECODER0_BASE_LO]); > + decoder_base = > + (((uint64_t)cache_mem[R_CXL_HDM_DECODER0_BASE_HI + i * hdm_inc] << 32) | > + cache_mem[R_CXL_HDM_DECODER0_BASE_LO + i * hdm_inc]); Alternatively easier to review as (matter of taste ?): decoder_base = deposit64(cache_mem[R_CXL_HDM_DECODER0_BASE_LO + i * hdm_inc], 32, 32, cache_mem[R_CXL_HDM_DECODER0_BASE_HI + i * hdm_inc]); Regardless: Reviewed-by: Philippe Mathieu-Daudé