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[88.21.68.240]) by smtp.gmail.com with ESMTPSA id d28sm3327375wrb.95.2019.09.24.06.43.00 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 24 Sep 2019 06:43:00 -0700 (PDT) Subject: Re: illegal hardware instruction during MIPS-I ELF linux useremulation To: Libo Zhou , Peter Maydell References: From: =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= Openpgp: id=89C1E78F601EE86C867495CBA2A3FD6EDEADC0DE; url=http://pgp.mit.edu/pks/lookup?op=get&search=0xA2A3FD6EDEADC0DE Message-ID: Date: Tue, 24 Sep 2019 15:42:59 +0200 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:60.0) Gecko/20100101 Thunderbird/60.7.0 MIME-Version: 1.0 In-Reply-To: Content-Language: en-US X-MC-Unique: aLIDyS95Pby1Y-JtU5WS9g-1 X-Mimecast-Spam-Score: 0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 207.211.31.81 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-devel , Aleksandar Markovic Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On 9/24/19 3:31 PM, Libo Zhou wrote: >>> I would start by using the QEMU gdbstub to connect a >>> MIPS-aware gdb. Then when the SIGILL arrives you can see >>> what instruction the guest program was trying to execute. >=20 >> Just tried it and found something interesting. >> I connected gdb-multiarch to QEMU gdbstub. gdb-multiarch's architecture = was set to mips:3000 automatically (and Wikipedia says r3k uses MIPS-I). >=20 >> When I did 'layout asm', and compared the instructions displayed against= test.s generated by my mipsel-linux-unknown-gcc, they appeared to be a lit= tle bit different. >=20 >> The 'store word' instruction in test.s is shown as a hex '0x7f......(don= 't remember the rest)'; >> 'load word' is shown as '0x5f......'; >> 'load immediate' is seen as 'addi'; >> 'j' as 'jr'; >=20 >> When I single-stepped the instructions, the SIGILL was thrown immediatel= y after the first unrecognized 0x7f......, which is supposed to be a store = word (sw). >=20 >> Hence, can I conclude that MIPS-I is not implemented in QEMU out of the = box? Or is it possible that my compiler doesn't implement MIPS-I correctly? >=20 > More updates about this. I just disassembled the unrecognized hex by hand= , and figured out that the store word and load word opcodes are not the sam= e as specified in translate.c. While the remaining fields of those unrecogn= ized instructions do match with the source and destination registers. What is your compiler/assembler versions (on both machines you used)?