Re: [PATCH v2 5/5] target/riscv: Add pointer mask support for instruction fetch

[liweiwei <liweiwei@iscas.ac.cn>]

On 2023/3/30 00:36, Richard Henderson wrote:
> On 3/28/23 20:23, Weiwei Li wrote:
>> Transform the fetch address in cpu_get_tb_cpu_state() when pointer
>> mask for instruction is enabled.
>> Enable PC-relative translation when J is enabled.
>>
>> Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
>> Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
>> ---
>>   target/riscv/cpu.c        |  4 ++++
>>   target/riscv/cpu.h        |  1 +
>>   target/riscv/cpu_helper.c | 20 +++++++++++++++++++-
>>   target/riscv/csr.c        |  2 --
>>   4 files changed, 24 insertions(+), 3 deletions(-)
>>
>> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
>> index 646fa31a59..99f0177c6d 100644
>> --- a/target/riscv/cpu.c
>> +++ b/target/riscv/cpu.c
>> @@ -1193,6 +1193,10 @@ static void riscv_cpu_realize(DeviceState 
>> *dev, Error **errp)
>>       #ifndef CONFIG_USER_ONLY
>> +    if(cpu->cfg.ext_j) {
>> +        cs->tcg_cflags |= CF_PCREL;
>> +    }
>
> "if ("
>
> Consider enabling it always for system mode.  The reason for the 
> existence of CF_PCREL is to improve performance with the guest 
> kernel's address space randomization.  Each guest process maps libc.so 
> (et al) at a different virtual address, and this allows those 
> translations to be shared.
>
> I would enable CF_PCREL in a separate patch from MMTE_*_PM_INSN.

OK. I'll update this in next version.

Regards,

Weiwei Li

>
>
> r~