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[83.50.68.71]) by smtp.gmail.com with ESMTPSA id z3sm6278170wmp.42.2022.02.20.12.06.41 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Sun, 20 Feb 2022 12:06:42 -0800 (PST) Message-ID: Date: Sun, 20 Feb 2022 21:06:41 +0100 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Macintosh; Intel Mac OS X 10.15; rv:91.0) Gecko/20100101 Thunderbird/91.6.0 Subject: Re: [PATCH v3 3/6] hw/openrisc/openrisc_sim: Use IRQ splitter when connecting UART Content-Language: en-US To: Stafford Horne , QEMU Development References: <20220219064210.3145381-1-shorne@gmail.com> <20220219064210.3145381-4-shorne@gmail.com> From: =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= In-Reply-To: <20220219064210.3145381-4-shorne@gmail.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit X-Host-Lookup-Failed: Reverse DNS lookup failed for 2a00:1450:4864:20::432 (failed) Received-SPF: pass client-ip=2a00:1450:4864:20::432; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-x432.google.com X-Spam_score_int: -6 X-Spam_score: -0.7 X-Spam_bar: / X-Spam_report: (-0.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, NICE_REPLY_A=-0.001, PDS_HP_HELO_NORDNS=0.659, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , Jia Liu Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On 19/2/22 07:42, Stafford Horne wrote: > Currently the OpenRISC SMP configuration only supports 2 cores due to > the UART IRQ routing being limited to 2 cores. As was done in commit > 1eeffbeb11 ("hw/openrisc/openrisc_sim: Use IRQ splitter when connecting > IRQ to multiple CPUs") we can use a splitter to wire more than 2 CPUs. > > This patch moves serial initialization out to it's own function and > uses a splitter to connect multiple CPU irq lines to the UART. > > Signed-off-by: Stafford Horne > --- > hw/openrisc/openrisc_sim.c | 32 ++++++++++++++++++++++++-------- > 1 file changed, 24 insertions(+), 8 deletions(-) > > diff --git a/hw/openrisc/openrisc_sim.c b/hw/openrisc/openrisc_sim.c > index d12b3e0c5e..5bfbac00f8 100644 > --- a/hw/openrisc/openrisc_sim.c > +++ b/hw/openrisc/openrisc_sim.c > @@ -137,6 +137,28 @@ static void openrisc_sim_ompic_init(hwaddr base, int num_cpus, > sysbus_mmio_map(s, 0, base); > } > > +static void openrisc_sim_serial_init(hwaddr base, int num_cpus, > + OpenRISCCPU *cpus[], int irq_pin) > +{ > + qemu_irq serial_irq; > + int i; > + > + if (num_cpus > 1) { > + DeviceState *splitter = qdev_new(TYPE_SPLIT_IRQ); > + qdev_prop_set_uint32(splitter, "num-lines", num_cpus); > + qdev_realize_and_unref(splitter, NULL, &error_fatal); > + for (i = 0; i < num_cpus; i++) { > + qdev_connect_gpio_out(splitter, i, get_cpu_irq(cpus, i, irq_pin)); > + } > + serial_irq = qdev_get_gpio_in(splitter, 0); > + } else { > + serial_irq = get_cpu_irq(cpus, 0, irq_pin); > + } Up to here the code seems a generic helper: or1k_cpus_connect_device(OpenRISCCPU *cpus[], unsigned num_cpus, unsigned irq_pin); > + serial_mm_init(get_system_memory(), base, 0, serial_irq, 115200, > + serial_hd(0), DEVICE_NATIVE_ENDIAN); This part specific to UART. > +} Anyhow, Reviewed-by: Philippe Mathieu-Daudé