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[176.184.14.96]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-434aa7a4e85sm18253945e9.5.2024.11.27.03.23.35 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 27 Nov 2024 03:23:37 -0800 (PST) Message-ID: Date: Wed, 27 Nov 2024 12:23:35 +0100 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v3 0/3] Introduce a new Write Protected pin inverted property To: =?UTF-8?Q?C=C3=A9dric_Le_Goater?= , Jamin Lin , Peter Maydell , Steven Lee , Troy Lee , Andrew Jeffery , Joel Stanley , Bin Meng , "open list:ASPEED BMCs" , "open list:All patches CC here" , "open list:SD (Secure Card)" Cc: troy_lee@aspeedtech.com, yunlin.tang@aspeedtech.com References: <20241114094839.4128404-1-jamin_lin@aspeedtech.com> <2e956389-289a-4806-8985-ab846d808736@kaod.org> Content-Language: en-US From: =?UTF-8?Q?Philippe_Mathieu-Daud=C3=A9?= In-Reply-To: <2e956389-289a-4806-8985-ab846d808736@kaod.org> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::32d; envelope-from=philmd@linaro.org; helo=mail-wm1-x32d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On 27/11/24 10:44, Cédric Le Goater wrote: > On 11/14/24 10:48, Jamin Lin wrote: >> change from v1: >> 1. Support RTC for AST2700. >> 2. Support SDHCI write protected pin inverted for AST2500 and AST2600. >> 3. Introduce Capabilities Register 2 for SD slot 0 and 1. >> 4. Support create flash devices via command line for AST1030. >> >> change from v2: >> replace wp-invert with wp-inverted and fix review issues. >> >> change from v3: >> 1. add reviewer suggestion about wp_inverted comment >> 2. AST2500 EVB does not need to set wp-inverted property of sdhci model >> >> https://github.com/AspeedTech-BMC/linux/blob/aspeed-master-v6.6/arch/arm/boot/dts/aspeed/aspeed-ast2500-evb.dts#L110 >> >> Jamin Lin (3): >>    hw/sd/sdhci: Fix coding style >>    hw/sd/sdhci: Introduce a new Write Protected pin inverted property >>    hw/arm/aspeed: Invert sdhci write protected pin for AST2600 EVB >> >>   hw/arm/aspeed.c         |  7 +++++ >>   hw/sd/sdhci.c           | 70 ++++++++++++++++++++++++++++------------- >>   include/hw/arm/aspeed.h |  1 + >>   include/hw/sd/sdhci.h   |  5 +++ >>   4 files changed, 61 insertions(+), 22 deletions(-) >> > > Philippe, > > I plan to queue patch 2-3 for QEMU 10.0. Is that ok for you ? Having to modify sdhci.c internals is dubious, since inversion occurs out of this block. If this is the soc/board layer, isn't better to model at this level? Smth like: -- >8 -- diff --git a/hw/arm/aspeed_ast2600.c b/hw/arm/aspeed_ast2600.c index be3eb70cdd7..aad9be66b75 100644 --- a/hw/arm/aspeed_ast2600.c +++ b/hw/arm/aspeed_ast2600.c @@ -559,8 +559,9 @@ static void aspeed_soc_ast2600_realize(DeviceState *dev, Error **errp) } aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->sdhci), 0, sc->memmap[ASPEED_DEV_SDHCI]); + irq = aspeed_soc_get_irq(s, ASPEED_DEV_SDHCI); sysbus_connect_irq(SYS_BUS_DEVICE(&s->sdhci), 0, - aspeed_soc_get_irq(s, ASPEED_DEV_SDHCI)); + sc->sdhci_wp_inverted ? qemu_irq_invert(irq) : irq); /* eMMC */ if (!sysbus_realize(SYS_BUS_DEVICE(&s->emmc), errp)) { ---