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([2602:47:d48c:8101:9d81:5b04:51d7:acae]) by smtp.gmail.com with ESMTPSA id 84-20020a621657000000b0058124f92399sm1418039pfw.219.2023.01.06.11.33.21 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 06 Jan 2023 11:33:22 -0800 (PST) Message-ID: Date: Fri, 6 Jan 2023 11:33:20 -0800 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.4.2 Subject: Re: [RFC PATCH 16/40] target/arm: Represent the entire MPIDR_EL1 Content-Language: en-US To: Peter Maydell Cc: qemu-devel@nongnu.org, pbonzini@redhat.com, berrange@redhat.com, eduardo@habkost.net, armbru@redhat.com, ajones@ventanamicro.com, alex.bennee@linaro.org References: <20230103181646.55711-1-richard.henderson@linaro.org> <20230103181646.55711-17-richard.henderson@linaro.org> From: Richard Henderson In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=2607:f8b0:4864:20::634; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x634.google.com X-Spam_score_int: -49 X-Spam_score: -5.0 X-Spam_bar: ----- X-Spam_report: (-5.0 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, NICE_REPLY_A=-2.939, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On 1/6/23 11:16, Peter Maydell wrote: > On Tue, 3 Jan 2023 at 18:24, Richard Henderson > wrote: >> >> Replace ARMCPU.mp_affinity with CPUARMState.cp15.mpidr_el1, >> setting the additional bits as required. In particular, >> always set the U bit when there is only one cpu in the system. >> Remove the mp_is_up bit which attempted to do the same thing. >> >> Signed-off-by: Richard Henderson >> --- >> target/arm/cpu.h | 7 ++-- >> target/arm/cpu.c | 80 +++++++++++++++++++++++++++++++++++++------- >> target/arm/cpu_tcg.c | 1 - >> target/arm/helper.c | 25 ++------------ >> target/arm/hvf/hvf.c | 2 +- >> target/arm/kvm64.c | 4 +-- >> 6 files changed, 75 insertions(+), 44 deletions(-) > > Based purely on the diffstat it's not super-obvious why this > is an improvement. What's the rationale ? It gets rid of cpu->mp_is_up, set only by cortex-r5, and then generalizes. > Side note, we don't currently handle the MT bit, where some > CPUs end up putting the cpu number in the Aff1 field rather > than Aff0. We ideally ought to handle that too. Would that be set by the board as well? I don't think we model cpu packages/clusters/whatchacallums at that level currently. r~