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[174.21.81.121]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-719090d0b14sm3483438b3a.215.2024.09.11.16.24.01 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 11 Sep 2024 16:24:02 -0700 (PDT) Message-ID: Date: Wed, 11 Sep 2024 16:24:00 -0700 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v4 11/12] tcg/riscv: Implement vector roti/v/x ops To: LIU Zhiwei , qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, palmer@dabbelt.com, alistair.francis@wdc.com, dbarboza@ventanamicro.com, liwei1518@gmail.com, bmeng.cn@gmail.com, TANG Tiancheng References: <20240911132630.461-1-zhiwei_liu@linux.alibaba.com> <20240911132630.461-12-zhiwei_liu@linux.alibaba.com> Content-Language: en-US From: Richard Henderson In-Reply-To: <20240911132630.461-12-zhiwei_liu@linux.alibaba.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=2607:f8b0:4864:20::429; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x429.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On 9/11/24 06:26, LIU Zhiwei wrote: > From: TANG Tiancheng > > Signed-off-by: TANG Tiancheng > Reviewed-by: Liu Zhiwei > --- > tcg/riscv/tcg-target.c.inc | 35 +++++++++++++++++++++++++++++++++++ > tcg/riscv/tcg-target.h | 6 +++--- > 2 files changed, 38 insertions(+), 3 deletions(-) > > diff --git a/tcg/riscv/tcg-target.c.inc b/tcg/riscv/tcg-target.c.inc > index 16785ebe8e..afc9747780 100644 > --- a/tcg/riscv/tcg-target.c.inc > +++ b/tcg/riscv/tcg-target.c.inc > @@ -2494,6 +2494,33 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc, > set_vtype_len_sew(s, type, vece); > tcg_out_vshifti(s, OPC_VSRA_VI, OPC_VSRA_VX, a0, a1, a2); > break; > + case INDEX_op_rotli_vec: > + set_vtype_len_sew(s, type, vece); > + tcg_out_vshifti(s, OPC_VSLL_VI, OPC_VSLL_VX, TCG_REG_V0, a1, a2); > + tcg_out_vshifti(s, OPC_VSRL_VI, OPC_VSRL_VX, a0, a1, -a2); You will want to mask -a2, because otherwise it will always fail to match imm < 32 within tcg_out_vshifti: -a2 & ((8 << vece) - 1) > + case INDEX_op_rotlv_vec: > + set_vtype_len_sew(s, type, vece); > + tcg_out_opc_vv(s, OPC_VSLL_VV, TCG_REG_V0, a1, a2, true); > + tcg_out_opc_vi(s, OPC_VRSUB_VI, TCG_REG_V0, a2, 0, true); > + tcg_out_opc_vv(s, OPC_VSRL_VV, a0, a1, TCG_REG_V0, true); You have written to V0 twice, clobbering the result. Need to swap the shifts: vrsub.vi v0, a2, 0 vsrl.vv v0, a1, v0 vsll.vv a0, a1, a2 vor.vv a0, a0, v0 r~