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([2400:4050:a840:1e00:4457:c267:5e09:481b]) by smtp.gmail.com with ESMTPSA id u2-20020a17090282c200b001a4edbabad3sm6489548plz.230.2023.04.24.04.46.37 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 24 Apr 2023 04:46:40 -0700 (PDT) Message-ID: Date: Mon, 24 Apr 2023 20:46:36 +0900 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux aarch64; rv:102.0) Gecko/20100101 Thunderbird/102.10.0 Subject: Re: [PATCH v3 06/47] igb: Clear IMS bits when committing ICR access Content-Language: en-US To: Sriram Yagnaraman Cc: Jason Wang , Dmitry Fleytman , "Michael S . Tsirkin" , =?UTF-8?Q?Alex_Benn=c3=a9e?= , =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= , Thomas Huth , Wainer dos Santos Moschetta , Beraldo Leal , Cleber Rosa , Laurent Vivier , Paolo Bonzini , "qemu-devel@nongnu.org" , Tomasz Dzieciol References: <20230423041833.5302-1-akihiko.odaki@daynix.com> <20230423041833.5302-7-akihiko.odaki@daynix.com> <410c76a1-8d1d-1835-6676-83e913f5ae24@daynix.com> From: Akihiko Odaki In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit Received-SPF: none client-ip=2607:f8b0:4864:20::42a; envelope-from=akihiko.odaki@daynix.com; helo=mail-pf1-x42a.google.com X-Spam_score_int: -30 X-Spam_score: -3.1 X-Spam_bar: --- X-Spam_report: (-3.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, NICE_REPLY_A=-1.194, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_NONE=0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On 2023/04/24 20:23, Sriram Yagnaraman wrote: > >> -----Original Message----- >> From: Akihiko Odaki >> Sent: Monday, 24 April 2023 12:52 >> To: Sriram Yagnaraman >> Cc: Jason Wang ; Dmitry Fleytman >> ; Michael S . Tsirkin ; Alex >> Bennée ; Philippe Mathieu-Daudé >> ; Thomas Huth ; Wainer dos Santos >> Moschetta ; Beraldo Leal ; >> Cleber Rosa ; Laurent Vivier ; Paolo >> Bonzini ; qemu-devel@nongnu.org; Tomasz Dzieciol >> >> Subject: Re: [PATCH v3 06/47] igb: Clear IMS bits when committing ICR access >> >> On 2023/04/24 18:29, Sriram Yagnaraman wrote: >>>> -----Original Message----- >>>> From: Akihiko Odaki >>>> Sent: Sunday, 23 April 2023 06:18 >>>> Cc: Sriram Yagnaraman ; Jason Wang >>>> ; Dmitry Fleytman ; >>>> Michael S . Tsirkin ; Alex Bennée >>>> ; Philippe Mathieu-Daudé ; >>>> Thomas Huth ; Wainer dos Santos Moschetta >>>> ; Beraldo Leal ; Cleber Rosa >>>> ; Laurent Vivier ; Paolo >>>> Bonzini ; qemu-devel@nongnu.org; Tomasz >> Dzieciol >>>> ; Akihiko Odaki >>>> >>>> Subject: [PATCH v3 06/47] igb: Clear IMS bits when committing ICR >>>> access >>>> >>>> The datasheet says contradicting statements regarding ICR accesses so >>>> it is not reliable to determine the behavior of ICR accesses. >>>> However, e1000e does clear IMS bits when reading ICR accesses and >>>> Linux also expects ICR accesses will clear IMS bits according to: >>>> https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tr >>>> ee/drivers/ >>>> net/ethernet/intel/igb/igb_main.c?h=v6.2#n8048 >>>> >>>> Fixes: 3a977deebe ("Intrdocue igb device emulation") >>>> Signed-off-by: Akihiko Odaki >>>> --- >>>> hw/net/igb_core.c | 8 ++++---- >>>> 1 file changed, 4 insertions(+), 4 deletions(-) >>>> >>>> diff --git a/hw/net/igb_core.c b/hw/net/igb_core.c index >>>> 96a118b6c1..eaca5bd2b6 100644 >>>> --- a/hw/net/igb_core.c >>>> +++ b/hw/net/igb_core.c >>>> @@ -2452,16 +2452,16 @@ igb_set_ims(IGBCore *core, int index, >>>> uint32_t >>>> val) static void igb_commit_icr(IGBCore *core) { >>>> /* >>>> - * If GPIE.NSICR = 0, then the copy of IAM to IMS will occur only if at >>>> + * If GPIE.NSICR = 0, then the clear of IMS will occur only if >>>> + at >>>> * least one bit is set in the IMS and there is a true interrupt as >>>> * reflected in ICR.INTA. >>>> */ >>>> if ((core->mac[GPIE] & E1000_GPIE_NSICR) || >>>> (core->mac[IMS] && (core->mac[ICR] & E1000_ICR_INT_ASSERTED))) { >>>> - igb_set_ims(core, IMS, core->mac[IAM]); >>>> - } else { >>>> - igb_update_interrupt_state(core); >>>> + igb_clear_ims_bits(core, core->mac[IAM]); >>>> } >>>> + >>>> + igb_update_interrupt_state(core); >>>> } >>>> >>>> static void igb_set_icr(IGBCore *core, int index, uint32_t val) >>>> -- >>>> 2.40.0 >>> >>> Reviewed-by: Sriram Yagnaraman >>> >>> An additional question, should ICR be cleared if an actual interrupt was >> asserted? >>> (According to 7.3.2.11 GPIE: Non Selective Interrupt clear on read: >>> When set, every read of ICR clears it. When this bit is cleared, an ICR read >> causes it to be cleared only if an actual interrupt was asserted or IMS = 0b.) >> Something like this? >> >> That is handled in igb_commit_icr(), which is renamed to igb_nsicr() in patch >> "igb: Notify only new interrupts". >> > > Mm, I must be missing something, but I still don't see the ICR bits being cleared igb_commit_icr/igb_nsicr(). > For e.g. e1000e_mac_icr_read does this explicitly: > if ((core->mac[ICR] & E1000_ICR_ASSERTED) && > (core->mac[CTRL_EXT] & E1000_CTRL_EXT_IAME)) { > trace_e1000e_irq_icr_clear_iame(); > core->mac[ICR] = 0; > trace_e1000e_irq_icr_process_iame(); > e1000e_clear_ims_bits(core, core->mac[IAM]); > } Now I get it. This is indeed missing and needs to be handled, just as you suggested. > > >>> >>> diff --git a/hw/net/igb_core.c b/hw/net/igb_core.c index >>> eaca5bd2b6..aaaf80e4a3 100644 >>> --- a/hw/net/igb_core.c >>> +++ b/hw/net/igb_core.c >>> @@ -2529,6 +2529,9 @@ igb_mac_icr_read(IGBCore *core, int index) >>> } else if (core->mac[IMS] == 0) { >>> trace_e1000e_irq_icr_clear_zero_ims(); >>> core->mac[ICR] = 0; >>> + } else if (core->mac[ICR] & E1000_ICR_INT_ASSERTED) { >>> + e1000e_irq_icr_clear_iame(); >>> + core->mac[ICR] = 0; >>> } else if (!msix_enabled(core->owner)) { >>> trace_e1000e_irq_icr_clear_nonmsix_icr_read(); >>> core->mac[ICR] = 0;