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bh=QdNpFd2oH5cIQMeTtqATMLbaxbn3/k5IR+f4n527Q+I=; b=OvAeF9ZUmrGxrLqVa3Z3PEailVRdUfEFyGiSq9Jaaj0c0eW5CdIgqN8pL95KEjVEesXyzH OYVIpLY7/P2pDWv6rfKGXFv4cmVCRLqzai71ig07gDWmbxu7yGmPW855NoUk2lFLB/QDqf wCNWAT1/ckM9+JdVV+IPNUXPofAsFUI= Received: from mimecast-mx01.redhat.com (mimecast-mx01.redhat.com [209.132.183.4]) (Using TLS) by relay.mimecast.com with ESMTP id us-mta-95-c93wPVNsOKOOz_iRRdyDCA-1; Wed, 17 Mar 2021 11:59:18 -0400 X-MC-Unique: c93wPVNsOKOOz_iRRdyDCA-1 Received: from smtp.corp.redhat.com (int-mx05.intmail.prod.int.phx2.redhat.com [10.5.11.15]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx01.redhat.com (Postfix) with ESMTPS id 43BE710CE790; Wed, 17 Mar 2021 15:59:17 +0000 (UTC) Received: from lacos-laptop-7.usersys.redhat.com (ovpn-113-112.ams2.redhat.com [10.36.113.112]) by smtp.corp.redhat.com (Postfix) with ESMTP id E37365D6A1; Wed, 17 Mar 2021 15:59:14 +0000 (UTC) Subject: Re: [RFC PATCH 5/8] qtest/libqos: Restrict CPU I/O instructions To: =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= , Richard Henderson , qemu-devel@nongnu.org References: <20210314232913.2607360-1-f4bug@amsat.org> <20210314232913.2607360-6-f4bug@amsat.org> <66630c68-d8ff-45ca-24e6-bbef1fc566ee@linaro.org> <235ffc43-288b-85aa-29f9-8f23e596674b@amsat.org> From: Laszlo Ersek Message-ID: Date: Wed, 17 Mar 2021 16:59:13 +0100 MIME-Version: 1.0 In-Reply-To: <235ffc43-288b-85aa-29f9-8f23e596674b@amsat.org> X-Scanned-By: MIMEDefang 2.79 on 10.5.11.15 Authentication-Results: relay.mimecast.com; auth=pass smtp.auth=CUSA124A263 smtp.mailfrom=lersek@redhat.com X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=216.205.24.124; envelope-from=lersek@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -29 X-Spam_score: -3.0 X-Spam_bar: --- X-Spam_report: (-3.0 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.251, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Laurent Vivier , Peter Maydell , Thomas Huth , Claudio Fontana , Paolo Bonzini , =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= , Gerd Hoffmann Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On 03/16/21 16:55, Philippe Mathieu-Daudé wrote: > Hi Richard and Laszlo, > > On 3/16/21 4:43 PM, Richard Henderson wrote: >> On 3/16/21 9:37 AM, Laszlo Ersek wrote: >>> (+Peter, comment below) >>> >>> On 03/15/21 00:29, Philippe Mathieu-Daudé wrote: >>>> Restrict CPU I/O instructions to architectures providing >>>> I/O bus. >>>> >>>> Signed-off-by: Philippe Mathieu-Daudé >>>> --- >>>>   tests/qtest/libqos/fw_cfg.h | 3 +++ >>>>   tests/qtest/libqos/fw_cfg.c | 2 ++ >>>>   2 files changed, 5 insertions(+) >>>> >>>> diff --git a/tests/qtest/libqos/fw_cfg.h b/tests/qtest/libqos/fw_cfg.h >>>> index c6a7cf8cf05..3bfb6d6d55b 100644 >>>> --- a/tests/qtest/libqos/fw_cfg.h >>>> +++ b/tests/qtest/libqos/fw_cfg.h >>>> @@ -36,6 +36,8 @@ size_t qfw_cfg_get_file(QFWCFG *fw_cfg, const char >>>> *filename, >>>>     QFWCFG *mm_fw_cfg_init(QTestState *qts, uint64_t base); >>>>   void mm_fw_cfg_uninit(QFWCFG *fw_cfg); >>>> + >>>> +#ifdef TARGET_HAS_IOPORT >>>>   QFWCFG *io_fw_cfg_init(QTestState *qts, uint16_t base); >>>>   void io_fw_cfg_uninit(QFWCFG *fw_cfg); >>>>   @@ -48,6 +50,7 @@ static inline void pc_fw_cfg_uninit(QFWCFG *fw_cfg) >>>>   { >>>>       io_fw_cfg_uninit(fw_cfg); >>>>   } >>>> +#endif /* TARGET_HAS_IOPORT */ >>>>     G_DEFINE_AUTOPTR_CLEANUP_FUNC(QFWCFG, mm_fw_cfg_uninit) >>>>   diff --git a/tests/qtest/libqos/fw_cfg.c b/tests/qtest/libqos/fw_cfg.c >>>> index 6b8e1babe51..db2b83f5212 100644 >>>> --- a/tests/qtest/libqos/fw_cfg.c >>>> +++ b/tests/qtest/libqos/fw_cfg.c >>>> @@ -131,6 +131,7 @@ void mm_fw_cfg_uninit(QFWCFG *fw_cfg) >>>>       g_free(fw_cfg); >>>>   } >>>>   +#ifdef TARGET_HAS_IOPORT >>>>   static void io_fw_cfg_select(QFWCFG *fw_cfg, uint16_t key) >>>>   { >>>>       qtest_outw(fw_cfg->qts, fw_cfg->base, key); >>>> @@ -162,3 +163,4 @@ void io_fw_cfg_uninit(QFWCFG *fw_cfg) >>>>   { >>>>       g_free(fw_cfg); >>>>   } >>>> +#endif /* TARGET_HAS_IOPORT */ >>>> >>> >>> I'm not sure the macro name is ideal; the PCI host on aarch64/"virt" >>> emulates IO Ports (it's possible to allocate PCI IO resources on >>> "virt"). From patch#3, TARGET_HAS_IOPORT does not seem to extend to >>> arm64. >> >> Correct, aarch64 has memory-mapped pci io resources, they are not on a >> separate ioport address space as for x86 and avr. > > I first wrote TARGET_CPU_HAS_IOPORT but realized architecture > and CPU are linked, so I elided _CPU_. > > What I'd like to clear from the QTest API is the idea that the CPU has > direct access to the I/O bus via I/O specific instructions. > > Any machine able to use a host <-> PCI bus chipset is able to access > the I/O function from the PCI bus. > > The fact that on X86 the first PCI function is wired to the same I/O > bus than the CPU is a machine implementation detail. > > When accessing PCI I/O ressources on Aarch64, you don't have to use > dedicated I/O instructions. > > Anyway for now Thomas discarded this series, as QTest is a generic API, > and we never had to worry about mixing address spaces so far, so not in > a hurry to clean this (although it would be useful to change address > space to access DMA or secure-CPU-view from QTest). If this is about an "IO Bus" or "IO instructions", then we should call the macro TARGET_HAS_IO_BUS or "TARGET_ISA_HAS_IO" (or "TARGET_HAS_IO_INSNS"), or something like those. My only confusion was about the "IO Port" expression in the macro name; the idea is OK from my perspective otherwise. Thanks Laszlo