From: Richard Henderson <richard.henderson@linaro.org>
To: Gabriel Brookman <brookmangabriel@gmail.com>, qemu-devel@nongnu.org
Cc: "Helge Deller" <deller@gmx.de>,
"Peter Maydell" <peter.maydell@linaro.org>,
"Andreas Hüttel" <andreas.huettel@ur.de>
Subject: Re: [PATCH] target/hppa: correct size bit parity for fmpyadd
Date: Thu, 9 Oct 2025 14:23:33 -0700 [thread overview]
Message-ID: <b5e928a2-f4ae-4b24-a2c0-2f67442dff2e@linaro.org> (raw)
In-Reply-To: <20251009-hppa-correct-fmpyadd-size-bit-decoding-v1-1-f63bb6c3290c@gmail.com>
On 10/9/25 13:51, Gabriel Brookman wrote:
> For the fmpyadd instruction on the hppa architecture, there is a bit
> used to specify whether the instruction is operating on a 32 bit or 64
> bit floating point register. For most instructions, such a bit is 0 when
> operating on the smaller register and 1 when operating on the larger
> register. However, according to page 6-57 of the PA-RISC 1.1 Architecture
> and Instruction Set Reference Manual,
Annoyingly, page 6-57 doesn't actually mention the interpretation of the f bit at all.
However, I can see how the H specifier is processed in gas, and the confirmation of glibc
fixes is nice.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
next prev parent reply other threads:[~2025-10-09 21:24 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-10-09 20:51 [PATCH] target/hppa: correct size bit parity for fmpyadd Gabriel Brookman
2025-10-09 21:23 ` Richard Henderson [this message]
2025-10-09 21:30 ` [EXT] " Andreas K. Huettel
2025-10-09 21:32 ` Richard Henderson
2025-10-09 21:41 ` Helge Deller
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