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From: Andrew Jeffery <andrew@codeconstruct.com.au>
To: Coco Li <lixiaoyan@google.com>, clg@kaod.org
Cc: qemu-arm@nongnu.org, qemu-devel@nongnu.org, flwu@google.com,
	Peter Maydell	 <peter.maydell@linaro.org>
Subject: Re: [PATCH v1 1/5] hw/gpio: Add property for ASPEED GPIO in 32 bits basis
Date: Thu, 02 Oct 2025 08:54:01 +0930	[thread overview]
Message-ID: <b601f750adc19ea0fe8ec8f2c578f9f23d7259cc.camel@codeconstruct.com.au> (raw)
In-Reply-To: <20250925005832.3708492-2-lixiaoyan@google.com>

On Thu, 2025-09-25 at 00:58 +0000, Coco Li wrote:
> From: Felix Wu <flwu@google.com>
> 
> Added 32 bits property for ASPEED GPIO. Previously it can only be access in bitwise manner.
> 
> This change gives ASPEED similar behavior as Nuvoton.

I don't think this has adequately addressed my request on the prior
series:

https://lore.kernel.org/all/e244fdb5d2d889674a583df8f8b9bc4bf8d476f4.camel@codeconstruct.com.au/

Can you please improve the commit message?

I don't have any particular concern with the implementation, other than
understanding whether it's something that's reasonable to add to begin
with. The "sets" and their indexes are somewhat an implementation
detail. Exposing them might preclude a different implementation design,
though I'm also not sure why we'd change at this point.

Andrew

> 
> Signed-off-by: Felix Wu <flwu@google.com>
> ---
>  hw/gpio/aspeed_gpio.c | 57 +++++++++++++++++++++++++++++++++++++++++++
>  1 file changed, 57 insertions(+)
> 
> diff --git a/hw/gpio/aspeed_gpio.c b/hw/gpio/aspeed_gpio.c
> index 609a556908..2d78bf9515 100644
> --- a/hw/gpio/aspeed_gpio.c
> +++ b/hw/gpio/aspeed_gpio.c
> @@ -1308,6 +1308,57 @@ static void aspeed_gpio_2700_write(void *opaque, hwaddr offset,
>  }
>  
>  /* Setup functions */
> +static void aspeed_gpio_set_set(Object *obj, Visitor *v,
> +                                        const char *name, void *opaque,
> +                                        Error **errp)
> +{
> +    uint32_t set_val = 0;
> +    AspeedGPIOState *s = ASPEED_GPIO(obj);
> +    AspeedGPIOClass *agc = ASPEED_GPIO_GET_CLASS(s);
> +    int set_idx = 0;
> +
> +    if (!visit_type_uint32(v, name, &set_val, errp)) {
> +        return;
> +    }
> +
> +    if (sscanf(name, "gpio-set[%d]", &set_idx) != 1) {
> +        error_setg(errp, "%s: error reading %s", __func__, name);
> +        return;
> +    }
> +
> +    if (set_idx >= agc->nr_gpio_sets || set_idx < 0) {
> +        error_setg(errp, "%s: invalid set_idx %s", __func__, name);
> +        return;
> +    }
> +
> +    aspeed_gpio_update(s, &s->sets[set_idx], set_val,
> +                       ~s->sets[set_idx].direction);
> +}
> +
> +static void aspeed_gpio_get_set(Object *obj, Visitor *v,
> +                                        const char *name, void *opaque,
> +                                        Error **errp)
> +{
> +    uint32_t set_val = 0;
> +    AspeedGPIOState *s = ASPEED_GPIO(obj);
> +    AspeedGPIOClass *agc = ASPEED_GPIO_GET_CLASS(s);
> +    int set_idx = 0;
> +
> +    if (sscanf(name, "gpio-set[%d]", &set_idx) != 1) {
> +        error_setg(errp, "%s: error reading %s", __func__, name);
> +        return;
> +    }
> +
> +    if (set_idx >= agc->nr_gpio_sets || set_idx < 0) {
> +        error_setg(errp, "%s: invalid set_idx %s", __func__, name);
> +        return;
> +    }
> +
> +    set_val = s->sets[set_idx].data_value;
> +    visit_type_uint32(v, name, &set_val, errp);
> +}
> +
> +/****************** Setup functions ******************/
>  static const GPIOSetProperties ast2400_set_props[ASPEED_GPIO_MAX_NR_SETS] = {
>      [0] = {0xffffffff,  0xffffffff,  {"A", "B", "C", "D"} },
>      [1] = {0xffffffff,  0xffffffff,  {"E", "F", "G", "H"} },
> @@ -1435,6 +1486,12 @@ static void aspeed_gpio_init(Object *obj)
>              g_free(name);
>          }
>      }
> +
> +    for (int i = 0; i < agc->nr_gpio_sets; i++) {
> +        char *name = g_strdup_printf("gpio-set[%d]", i);
> +        object_property_add(obj, name, "uint32", aspeed_gpio_get_set,
> +        aspeed_gpio_set_set, NULL, NULL);
> +    }
>  }
>  
>  static const VMStateDescription vmstate_gpio_regs = {

  reply	other threads:[~2025-10-01 23:27 UTC|newest]

Thread overview: 14+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-09-25  0:58 [PATCH v1 0/5] Add Aspeed GPIO test and Support Nuvoton Serial GPIO Expansion (SGPIO) device Coco Li
2025-09-25  0:58 ` [PATCH v1 1/5] hw/gpio: Add property for ASPEED GPIO in 32 bits basis Coco Li
2025-10-01 23:24   ` Andrew Jeffery [this message]
2025-10-03 17:44     ` Coco Li
2025-10-13  0:28       ` Andrew Jeffery
2025-09-25  0:58 ` [PATCH v1 2/5] tests/qtest: Add qtest for for ASPEED GPIO gpio-set property Coco Li
2025-09-25  0:58 ` [PATCH v1 3/5] hw/arm/npcm8xx.c: Add all IRQ ENUMs Coco Li
2025-09-25  1:08   ` Philippe Mathieu-Daudé
2025-09-26 21:48     ` Coco Li
2025-09-29  9:46       ` Philippe Mathieu-Daudé
2025-09-25  0:58 ` [PATCH v1 4/5] hw/gpio/npcm8xx: Implement SIOX (SPGIO) device for NPCM without input pin logic Coco Li
2025-09-25  0:58 ` [PATCH v1 5/5] hw/gpio/npcm8xx: Implement npcm sgpio device " Coco Li
2025-09-25  1:10   ` Philippe Mathieu-Daudé
2025-09-26 21:49     ` Coco Li

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