[PATCH V4 0/4] Basic ASID2 Support

[PATCH V4 0/4] Basic ASID2 Support

[Jim MacArthur]

Added a line to the documentation mentioning that we can now support ASID2.

Changes in v4:
- Patch 3:
  - Added mention of ASID2 to docs/system/arm/emulation.rst.

Jim MacArthur (4):
  target/arm: Enable ID_AA64MMFR4_EL1 register.
  target/arm: Allow writes to FNG1, FNG0, A2
  target/arm/tcg/cpu64.c: Enable ASID2 for cpu_max
  tests: Add test for ASID2 and write/read of feature bits

 docs/system/arm/emulation.rst    |  1 +
 target/arm/cpu-features.h        |  7 +++
 target/arm/cpu-sysregs.h.inc     |  1 +
 target/arm/helper.c              | 10 ++++-
 target/arm/tcg/cpu64.c           |  4 ++
 tests/tcg/aarch64/system/asid2.c | 75 ++++++++++++++++++++++++++++++++
 6 files changed, 96 insertions(+), 2 deletions(-)
 create mode 100644 tests/tcg/aarch64/system/asid2.c

-- 
2.43.0

[PATCH V4 1/4] target/arm: Enable ID_AA64MMFR4_EL1 register.

[Jim MacArthur]

Signed-off-by: Jim MacArthur <jim.macarthur@linaro.org>
---
 target/arm/cpu-sysregs.h.inc | 1 +
 target/arm/helper.c          | 4 ++--
 2 files changed, 3 insertions(+), 2 deletions(-)

diff --git a/target/arm/cpu-sysregs.h.inc b/target/arm/cpu-sysregs.h.inc
index 2bb2861c62..2ba49d8478 100644
--- a/target/arm/cpu-sysregs.h.inc
+++ b/target/arm/cpu-sysregs.h.inc
@@ -14,6 +14,7 @@ DEF(ID_AA64MMFR0_EL1, 3, 0, 0, 7, 0)
 DEF(ID_AA64MMFR1_EL1, 3, 0, 0, 7, 1)
 DEF(ID_AA64MMFR2_EL1, 3, 0, 0, 7, 2)
 DEF(ID_AA64MMFR3_EL1, 3, 0, 0, 7, 3)
+DEF(ID_AA64MMFR4_EL1, 3, 0, 0, 7, 4)
 DEF(ID_PFR0_EL1, 3, 0, 0, 1, 0)
 DEF(ID_PFR1_EL1, 3, 0, 0, 1, 1)
 DEF(ID_DFR0_EL1, 3, 0, 0, 1, 2)
diff --git a/target/arm/helper.c b/target/arm/helper.c
index 27ebc6f29b..c20334fa65 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -6566,11 +6566,11 @@ void register_cp_regs_for_features(ARMCPU *cpu)
               .access = PL1_R, .type = ARM_CP_CONST,
               .accessfn = access_aa64_tid3,
               .resetvalue = GET_IDREG(isar, ID_AA64MMFR3) },
-            { .name = "ID_AA64MMFR4_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
+            { .name = "ID_AA64MMFR4_EL1", .state = ARM_CP_STATE_AA64,
               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 4,
               .access = PL1_R, .type = ARM_CP_CONST,
               .accessfn = access_aa64_tid3,
-              .resetvalue = 0 },
+              .resetvalue = GET_IDREG(isar, ID_AA64MMFR4) },
             { .name = "ID_AA64MMFR5_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 5,
               .access = PL1_R, .type = ARM_CP_CONST,
-- 
2.43.0

[PATCH V4 2/4] target/arm: Allow writes to FNG1, FNG0, A2

[Jim MacArthur]

This just allows read/write of three feature bits. ASID is still
ignored. Any writes to TTBR0_EL0 and TTBR1_EL0, including changing
the ASID, will still cause a complete flush of the TLB.

Signed-off-by: Jim MacArthur <jim.macarthur@linaro.org>
---
 target/arm/cpu-features.h | 7 +++++++
 target/arm/helper.c       | 6 ++++++
 2 files changed, 13 insertions(+)

diff --git a/target/arm/cpu-features.h b/target/arm/cpu-features.h
index 579fa8f8f4..d56bda9ce0 100644
--- a/target/arm/cpu-features.h
+++ b/target/arm/cpu-features.h
@@ -346,6 +346,8 @@ FIELD(ID_AA64MMFR3, SDERR, 52, 4)
 FIELD(ID_AA64MMFR3, ADERR, 56, 4)
 FIELD(ID_AA64MMFR3, SPEC_FPACC, 60, 4)
 
+FIELD(ID_AA64MMFR4, ASID2, 8, 4)
+
 FIELD(ID_AA64DFR0, DEBUGVER, 0, 4)
 FIELD(ID_AA64DFR0, TRACEVER, 4, 4)
 FIELD(ID_AA64DFR0, PMUVER, 8, 4)
@@ -1369,6 +1371,11 @@ static inline bool isar_feature_aa64_aie(const ARMISARegisters *id)
     return FIELD_EX64_IDREG(id, ID_AA64MMFR3, AIE) != 0;
 }
 
+static inline bool isar_feature_aa64_asid2(const ARMISARegisters *id)
+{
+    return FIELD_EX64_IDREG(id, ID_AA64MMFR4, ASID2) != 0;
+}
+
 static inline bool isar_feature_aa64_mec(const ARMISARegisters *id)
 {
     return FIELD_EX64_IDREG(id, ID_AA64MMFR3, MEC) != 0;
diff --git a/target/arm/helper.c b/target/arm/helper.c
index c20334fa65..7812a82bab 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -6102,6 +6102,9 @@ static void tcr2_el1_write(CPUARMState *env, const ARMCPRegInfo *ri,
     if (cpu_isar_feature(aa64_aie, cpu)) {
         valid_mask |= TCR2_AIE;
     }
+    if (cpu_isar_feature(aa64_asid2, cpu)) {
+        valid_mask |= TCR2_FNG1 | TCR2_FNG0 | TCR2_A2;
+    }
     value &= valid_mask;
     raw_write(env, ri, value);
 }
@@ -6121,6 +6124,9 @@ static void tcr2_el2_write(CPUARMState *env, const ARMCPRegInfo *ri,
     if (cpu_isar_feature(aa64_mec, cpu)) {
         valid_mask |= TCR2_AMEC0 | TCR2_AMEC1;
     }
+    if (cpu_isar_feature(aa64_asid2, cpu)) {
+        valid_mask |= TCR2_FNG1 | TCR2_FNG0 | TCR2_A2;
+    }
     value &= valid_mask;
     raw_write(env, ri, value);
 }
-- 
2.43.0

[PATCH V4 3/4] target/arm/tcg/cpu64.c: Enable ASID2 for cpu_max

[Jim MacArthur]

docs/system/arm/emulation.rst: Add ASID2

Signed-off-by: Jim MacArthur <jim.macarthur@linaro.org>
---
 docs/system/arm/emulation.rst | 1 +
 target/arm/tcg/cpu64.c        | 4 ++++
 2 files changed, 5 insertions(+)

diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst
index 31a5878a8f..3f30ea5a30 100644
--- a/docs/system/arm/emulation.rst
+++ b/docs/system/arm/emulation.rst
@@ -24,6 +24,7 @@ the following architecture extensions:
 - FEAT_AIE (Memory Attribute Index Enhancement)
 - FEAT_Armv9_Crypto (Armv9 Cryptographic Extension)
 - FEAT_ASID16 (16 bit ASID)
+- FEAT_ASID2 (Concurrent use of two ASIDs)
 - FEAT_ATS1A (Address Translation operations that ignore stage 1 permissions)
 - FEAT_BBM at level 2 (Translation table break-before-make levels)
 - FEAT_BF16 (AArch64 BFloat16 instructions)
diff --git a/target/arm/tcg/cpu64.c b/target/arm/tcg/cpu64.c
index 6871956382..ef4c0c8d73 100644
--- a/target/arm/tcg/cpu64.c
+++ b/target/arm/tcg/cpu64.c
@@ -1334,6 +1334,10 @@ void aarch64_max_tcg_initfn(Object *obj)
     t = FIELD_DP64(t, ID_AA64MMFR3, AIE, 1);      /* FEAT_AIE */
     SET_IDREG(isar, ID_AA64MMFR3, t);
 
+    t = GET_IDREG(isar, ID_AA64MMFR4);
+    t = FIELD_DP64(t, ID_AA64MMFR4, ASID2, 1);    /* FEAT_ASID2 */
+    SET_IDREG(isar, ID_AA64MMFR4, t);
+
     t = GET_IDREG(isar, ID_AA64ZFR0);
     t = FIELD_DP64(t, ID_AA64ZFR0, SVEVER, 2);    /* FEAT_SVE2p1 */
     t = FIELD_DP64(t, ID_AA64ZFR0, AES, 2);       /* FEAT_SVE_PMULL128 */
-- 
2.43.0

[PATCH V4 4/4] tests: Add test for ASID2 and write/read of feature bits

[Jim MacArthur]

Test for presence of ASID2; if it is, check FNG1, FNG0, and A2 are
writable, and read value shows the update. If not present, check these
read as RES0.

Signed-off-by: Jim MacArthur <jim.macarthur@linaro.org>
---
 tests/tcg/aarch64/system/asid2.c | 75 ++++++++++++++++++++++++++++++++
 1 file changed, 75 insertions(+)
 create mode 100644 tests/tcg/aarch64/system/asid2.c

diff --git a/tests/tcg/aarch64/system/asid2.c b/tests/tcg/aarch64/system/asid2.c
new file mode 100644
index 0000000000..a4887e4ce2
--- /dev/null
+++ b/tests/tcg/aarch64/system/asid2.c
@@ -0,0 +1,75 @@
+/*
+ * ASID2 Feature presence and enabled TCR2_EL1 bits test
+ *
+ * Copyright (c) 2025 Linaro Ltd
+ *
+ * SPDX-License-Identifier: GPL-2.0-or-later
+ */
+
+#include <stdint.h>
+#include <minilib.h>
+
+#define ID_AA64MMFR3_EL1 "S3_0_C0_C7_3"
+#define ID_AA64MMFR4_EL1 "S3_0_C0_C7_4"
+#define TCR2_EL1 "S3_0_C2_C0_3"
+
+int main()
+{
+    /*
+     * Test for presence of ASID2 and three feature bits enabled by it:
+     * https://developer.arm.com/documentation/109697/2025_09/Feature-descriptions/The-Armv9-5-architecture-extension
+     * Bits added are FNG1, FNG0, and A2. These should be RES0 if A2 is
+     * not enabled and read as the written value if A2 is enabled.
+     */
+
+    uint64_t out;
+    uint64_t idreg3;
+    uint64_t idreg4;
+    int tcr2_present;
+    int asid2_present;
+
+    /* Mask is FNG1, FNG0, and A2 */
+    const uint64_t feature_mask = (1ULL << 18 | 1ULL << 17 | 1ULL << 16);
+    const uint64_t in = feature_mask;
+
+    asm("mrs %[x1], " ID_AA64MMFR3_EL1 "\n\t"
+        : [x1] "=r" (idreg3));
+
+    tcr2_present = ((idreg3 & 0xF) != 0);
+
+    if (!tcr2_present) {
+        ml_printf("TCR2 is not present, cannot perform test");
+        return 0;
+    }
+
+    asm("mrs %[x1], " ID_AA64MMFR4_EL1 "\n\t"
+        : [x1] "=r" (idreg4));
+
+    asid2_present = ((idreg4 & 0xF00) != 0);
+
+    asm("msr " TCR2_EL1 ", %[x0]\n\t"
+        "mrs %[x1], " TCR2_EL1 "\n\t"
+        : [x1] "=r" (out)
+        : [x0] "r" (in));
+
+    if (asid2_present) {
+        if ((out & feature_mask) == in) {
+            ml_printf("OK\n");
+            return 0;
+        } else {
+            ml_printf("FAIL: ASID2 present, but read value %lx != "
+                      "written value %lx\n",
+                      out & feature_mask, in);
+            return 1;
+        }
+    } else {
+        if (out == 0) {
+            ml_printf("TCR2_EL1 reads as RES0 as expected\n");
+            return 0;
+        } else {
+            ml_printf("FAIL: ASID2, missing but read value %lx != 0\n",
+                      out & feature_mask, in);
+            return 1;
+        }
+    }
+}
-- 
2.43.0

Re: [PATCH V4 1/4] target/arm: Enable ID_AA64MMFR4_EL1 register.

[Gustavo Romero]

Hi Jim,

nit: usually we don't use period in the commit title.

On 12/2/25 09:00, Jim MacArthur wrote:
> Signed-off-by: Jim MacArthur <jim.macarthur@linaro.org>
> ---
>   target/arm/cpu-sysregs.h.inc | 1 +
>   target/arm/helper.c          | 4 ++--
>   2 files changed, 3 insertions(+), 2 deletions(-)
> 
> diff --git a/target/arm/cpu-sysregs.h.inc b/target/arm/cpu-sysregs.h.inc
> index 2bb2861c62..2ba49d8478 100644
> --- a/target/arm/cpu-sysregs.h.inc
> +++ b/target/arm/cpu-sysregs.h.inc
> @@ -14,6 +14,7 @@ DEF(ID_AA64MMFR0_EL1, 3, 0, 0, 7, 0)
>   DEF(ID_AA64MMFR1_EL1, 3, 0, 0, 7, 1)
>   DEF(ID_AA64MMFR2_EL1, 3, 0, 0, 7, 2)
>   DEF(ID_AA64MMFR3_EL1, 3, 0, 0, 7, 3)
> +DEF(ID_AA64MMFR4_EL1, 3, 0, 0, 7, 4)
>   DEF(ID_PFR0_EL1, 3, 0, 0, 1, 0)
>   DEF(ID_PFR1_EL1, 3, 0, 0, 1, 1)
>   DEF(ID_DFR0_EL1, 3, 0, 0, 1, 2)
> diff --git a/target/arm/helper.c b/target/arm/helper.c
> index 27ebc6f29b..c20334fa65 100644
> --- a/target/arm/helper.c
> +++ b/target/arm/helper.c
> @@ -6566,11 +6566,11 @@ void register_cp_regs_for_features(ARMCPU *cpu)
>                 .access = PL1_R, .type = ARM_CP_CONST,
>                 .accessfn = access_aa64_tid3,
>                 .resetvalue = GET_IDREG(isar, ID_AA64MMFR3) },
> -            { .name = "ID_AA64MMFR4_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
> +            { .name = "ID_AA64MMFR4_EL1", .state = ARM_CP_STATE_AA64,
>                 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 4,
>                 .access = PL1_R, .type = ARM_CP_CONST,
>                 .accessfn = access_aa64_tid3,
> -              .resetvalue = 0 },
> +              .resetvalue = GET_IDREG(isar, ID_AA64MMFR4) },
>               { .name = "ID_AA64MMFR5_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
>                 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 5,
>                 .access = PL1_R, .type = ARM_CP_CONST,

Reviewed-by: Gustavo Romero <gustavo.romero@linaro.org>

Re: [PATCH V4 2/4] target/arm: Allow writes to FNG1, FNG0, A2

[Gustavo Romero]

Hi Jim,

On 12/2/25 09:00, Jim MacArthur wrote:
> This just allows read/write of three feature bits. ASID is still
> ignored. Any writes to TTBR0_EL0 and TTBR1_EL0, including changing
> the ASID, will still cause a complete flush of the TLB.
> 
> Signed-off-by: Jim MacArthur <jim.macarthur@linaro.org>
> ---
>   target/arm/cpu-features.h | 7 +++++++
>   target/arm/helper.c       | 6 ++++++
>   2 files changed, 13 insertions(+)
> 
> diff --git a/target/arm/cpu-features.h b/target/arm/cpu-features.h
> index 579fa8f8f4..d56bda9ce0 100644
> --- a/target/arm/cpu-features.h
> +++ b/target/arm/cpu-features.h
> @@ -346,6 +346,8 @@ FIELD(ID_AA64MMFR3, SDERR, 52, 4)
>   FIELD(ID_AA64MMFR3, ADERR, 56, 4)
>   FIELD(ID_AA64MMFR3, SPEC_FPACC, 60, 4)
>   
> +FIELD(ID_AA64MMFR4, ASID2, 8, 4)
> +
>   FIELD(ID_AA64DFR0, DEBUGVER, 0, 4)
>   FIELD(ID_AA64DFR0, TRACEVER, 4, 4)
>   FIELD(ID_AA64DFR0, PMUVER, 8, 4)
> @@ -1369,6 +1371,11 @@ static inline bool isar_feature_aa64_aie(const ARMISARegisters *id)
>       return FIELD_EX64_IDREG(id, ID_AA64MMFR3, AIE) != 0;
>   }
>   
> +static inline bool isar_feature_aa64_asid2(const ARMISARegisters *id)
> +{
> +    return FIELD_EX64_IDREG(id, ID_AA64MMFR4, ASID2) != 0;
> +}
> +
>   static inline bool isar_feature_aa64_mec(const ARMISARegisters *id)
>   {
>       return FIELD_EX64_IDREG(id, ID_AA64MMFR3, MEC) != 0;
> diff --git a/target/arm/helper.c b/target/arm/helper.c
> index c20334fa65..7812a82bab 100644
> --- a/target/arm/helper.c
> +++ b/target/arm/helper.c
> @@ -6102,6 +6102,9 @@ static void tcr2_el1_write(CPUARMState *env, const ARMCPRegInfo *ri,
>       if (cpu_isar_feature(aa64_aie, cpu)) {
>           valid_mask |= TCR2_AIE;
>       }
> +    if (cpu_isar_feature(aa64_asid2, cpu)) {
> +        valid_mask |= TCR2_FNG1 | TCR2_FNG0 | TCR2_A2;
> +    }
>       value &= valid_mask;
>       raw_write(env, ri, value);
>   }
> @@ -6121,6 +6124,9 @@ static void tcr2_el2_write(CPUARMState *env, const ARMCPRegInfo *ri,
>       if (cpu_isar_feature(aa64_mec, cpu)) {
>           valid_mask |= TCR2_AMEC0 | TCR2_AMEC1;
>       }
> +    if (cpu_isar_feature(aa64_asid2, cpu)) {
> +        valid_mask |= TCR2_FNG1 | TCR2_FNG0 | TCR2_A2;
> +    }
>       value &= valid_mask;
>       raw_write(env, ri, value);
>   }

Afaics, we are not flushing the TLB here like we do for TCR_ELx (in vmsa_tcr_el12_write) before
we call raw_write(). Since here we could be changing the A2 & friends bits, which can change
the value of the ASID being using (like the TCR_ELx.A1 bit), I believe we should flush the TLB
explicitly here like we do in vmsa_tcr_el12_write().

@rth wdyt?


Cheers,
Gustavo

Re: [PATCH V4 3/4] target/arm/tcg/cpu64.c: Enable ASID2 for cpu_max

[Gustavo Romero]

Hi Jim,

On 12/2/25 09:00, Jim MacArthur wrote:
> docs/system/arm/emulation.rst: Add ASID2
> 
> Signed-off-by: Jim MacArthur <jim.macarthur@linaro.org>
> ---
>   docs/system/arm/emulation.rst | 1 +
>   target/arm/tcg/cpu64.c        | 4 ++++
>   2 files changed, 5 insertions(+)
> 
> diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst
> index 31a5878a8f..3f30ea5a30 100644
> --- a/docs/system/arm/emulation.rst
> +++ b/docs/system/arm/emulation.rst
> @@ -24,6 +24,7 @@ the following architecture extensions:
>   - FEAT_AIE (Memory Attribute Index Enhancement)
>   - FEAT_Armv9_Crypto (Armv9 Cryptographic Extension)
>   - FEAT_ASID16 (16 bit ASID)
> +- FEAT_ASID2 (Concurrent use of two ASIDs)
>   - FEAT_ATS1A (Address Translation operations that ignore stage 1 permissions)
>   - FEAT_BBM at level 2 (Translation table break-before-make levels)
>   - FEAT_BF16 (AArch64 BFloat16 instructions)
> diff --git a/target/arm/tcg/cpu64.c b/target/arm/tcg/cpu64.c
> index 6871956382..ef4c0c8d73 100644
> --- a/target/arm/tcg/cpu64.c
> +++ b/target/arm/tcg/cpu64.c
> @@ -1334,6 +1334,10 @@ void aarch64_max_tcg_initfn(Object *obj)
>       t = FIELD_DP64(t, ID_AA64MMFR3, AIE, 1);      /* FEAT_AIE */
>       SET_IDREG(isar, ID_AA64MMFR3, t);
>   
> +    t = GET_IDREG(isar, ID_AA64MMFR4);
> +    t = FIELD_DP64(t, ID_AA64MMFR4, ASID2, 1);    /* FEAT_ASID2 */
> +    SET_IDREG(isar, ID_AA64MMFR4, t);
> +
>       t = GET_IDREG(isar, ID_AA64ZFR0);
>       t = FIELD_DP64(t, ID_AA64ZFR0, SVEVER, 2);    /* FEAT_SVE2p1 */
>       t = FIELD_DP64(t, ID_AA64ZFR0, AES, 2);       /* FEAT_SVE_PMULL128 */

Reviewed-by: Gustavo Romero <gustavo.romero@linaro.org>

Re: [PATCH V4 4/4] tests: Add test for ASID2 and write/read of feature bits

[Gustavo Romero]

Hi Jim,

On 12/2/25 09:00, Jim MacArthur wrote:
> Test for presence of ASID2; if it is, check FNG1, FNG0, and A2 are
> writable, and read value shows the update. If not present, check these
> read as RES0.
> 
> Signed-off-by: Jim MacArthur <jim.macarthur@linaro.org>
> ---
>   tests/tcg/aarch64/system/asid2.c | 75 ++++++++++++++++++++++++++++++++
>   1 file changed, 75 insertions(+)
>   create mode 100644 tests/tcg/aarch64/system/asid2.c
> 
> diff --git a/tests/tcg/aarch64/system/asid2.c b/tests/tcg/aarch64/system/asid2.c
> new file mode 100644
> index 0000000000..a4887e4ce2
> --- /dev/null
> +++ b/tests/tcg/aarch64/system/asid2.c
> @@ -0,0 +1,75 @@
> +/*
> + * ASID2 Feature presence and enabled TCR2_EL1 bits test
> + *
> + * Copyright (c) 2025 Linaro Ltd
> + *
> + * SPDX-License-Identifier: GPL-2.0-or-later

The SPDX tag must go in the first line, except in script sources, where it goes
after the shebang line.


+ */
> +
> +#include <stdint.h>
> +#include <minilib.h>
> +
> +#define ID_AA64MMFR3_EL1 "S3_0_C0_C7_3"
> +#define ID_AA64MMFR4_EL1 "S3_0_C0_C7_4"
> +#define TCR2_EL1 "S3_0_C2_C0_3"
> +
> +int main()
> +{
> +    /*
> +     * Test for presence of ASID2 and three feature bits enabled by it:
> +     * https://developer.arm.com/documentation/109697/2025_09/Feature-descriptions/The-Armv9-5-architecture-extension
> +     * Bits added are FNG1, FNG0, and A2. These should be RES0 if A2 is
> +     * not enabled and read as the written value if A2 is enabled.
> +     */
> +
> +    uint64_t out;
> +    uint64_t idreg3;
> +    uint64_t idreg4;
> +    int tcr2_present;
> +    int asid2_present;
> +
> +    /* Mask is FNG1, FNG0, and A2 */
> +    const uint64_t feature_mask = (1ULL << 18 | 1ULL << 17 | 1ULL << 16);
> +    const uint64_t in = feature_mask;
> +
> +    asm("mrs %[x1], " ID_AA64MMFR3_EL1 "\n\t"
> +        : [x1] "=r" (idreg3));

You can use the same name for the asm label as the one used for the C variable to
ease even further reading the code, so it's ok to do:

asm("mrs %[idreg3], " ID_AA64MMFR3_EL1 "\n\t"
      : [idreg3] "=r" (idreg3));


Likewise for all the other uses of asm() below.

Otherwise the test LGTM.


Cheers,
Gustavo

> +    tcr2_present = ((idreg3 & 0xF) != 0);
> +
> +    if (!tcr2_present) {
> +        ml_printf("TCR2 is not present, cannot perform test");
> +        return 0;
> +    }
> +
> +    asm("mrs %[x1], " ID_AA64MMFR4_EL1 "\n\t"
> +        : [x1] "=r" (idreg4));
> +
> +    asid2_present = ((idreg4 & 0xF00) != 0);
> +
> +    asm("msr " TCR2_EL1 ", %[x0]\n\t"
> +        "mrs %[x1], " TCR2_EL1 "\n\t"
> +        : [x1] "=r" (out)
> +        : [x0] "r" (in));
> +
> +    if (asid2_present) {
> +        if ((out & feature_mask) == in) {
> +            ml_printf("OK\n");
> +            return 0;
> +        } else {
> +            ml_printf("FAIL: ASID2 present, but read value %lx != "
> +                      "written value %lx\n",
> +                      out & feature_mask, in);
> +            return 1;
> +        }
> +    } else {
> +        if (out == 0) {
> +            ml_printf("TCR2_EL1 reads as RES0 as expected\n");
> +            return 0;
> +        } else {
> +            ml_printf("FAIL: ASID2, missing but read value %lx != 0\n",
> +                      out & feature_mask, in);
> +            return 1;
> +        }
> +    }
> +}

Re: [PATCH V4 2/4] target/arm: Allow writes to FNG1, FNG0, A2

[Jim MacArthur]

On Tue, 2 Dec 2025 at 14:29, Gustavo Romero <gustavo.romero@linaro.org> wrote:
> Afaics, we are not flushing the TLB here like we do for TCR_ELx (in vmsa_tcr_el12_write) before
> we call raw_write(). Since here we could be changing the A2 & friends bits, which can change
> the value of the ASID being using (like the TCR_ELx.A1 bit), I believe we should flush the TLB
> explicitly here like we do in vmsa_tcr_el12_write().
>
> @rth wdyt?

I agree; the guest could reasonably expect TLB entries previously in
use to stop being matched. In any case, I don't imagine flushing the
TLB here will be a significant performance problem. Good spot!

Jim