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To: andrew@daynix.com, qemu-devel@nongnu.org References: <20200506212645.894533-1-andrew@daynix.com> From: Jason Wang Message-ID: Date: Fri, 8 May 2020 10:21:21 +0800 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.7.0 MIME-Version: 1.0 In-Reply-To: <20200506212645.894533-1-andrew@daynix.com> Content-Language: en-US X-Scanned-By: MIMEDefang 2.79 on 10.5.11.12 X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: quoted-printable Received-SPF: pass client-ip=205.139.110.61; envelope-from=jasowang@redhat.com; helo=us-smtp-delivery-1.mimecast.com X-detected-operating-system: by eggs.gnu.org: First seen = 2020/05/07 22:21:30 X-ACL-Warn: Detected OS = Linux 2.2.x-3.x [generic] X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=-0.001, SPF_PASS=-0.001, URIBL_BLOCKED=0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: dmitry.fleytman@gmail.com Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On 2020/5/7 =E4=B8=8A=E5=8D=885:26, andrew@daynix.com wrote: > From: Andrew Melnychenko > > Buglink: https://bugzilla.redhat.com/show_bug.cgi?id=3D1707441 > Added ICR clearing if there is IMS bit - according to the note by > section 13.3.27 of the 8257X developers manual. > > Signed-off-by: Andrew Melnychenko > --- > hw/net/e1000e_core.c | 9 +++++++++ > hw/net/trace-events | 1 + > 2 files changed, 10 insertions(+) > > diff --git a/hw/net/e1000e_core.c b/hw/net/e1000e_core.c > index d5676871fa..302e99ff46 100644 > --- a/hw/net/e1000e_core.c > +++ b/hw/net/e1000e_core.c > @@ -2624,6 +2624,15 @@ e1000e_mac_icr_read(E1000ECore *core, int index) > e1000e_clear_ims_bits(core, core->mac[IAM]); > } > =20 > + /* > + * PCIe* GbE Controllers Open Source Software Developer's Manual > + * 13.3.27 Interrupt Cause Read Register > + */ Hi Andrew: Which version of the manual did you use? I try to use the one mentioned=20 in e1000e.c which is=20 http://www.intel.com/content/dam/doc/datasheet/82574l-gbe-controller-datash= eet.pdf. But I couldn't find chapter 13.3.27. Thanks > + if (core->mac[ICR] & core->mac[IMS]) { > + trace_e1000e_irq_icr_clear_icr_bit_ims(core->mac[ICR], core->mac= [IMS]); > + core->mac[ICR] =3D 0; > + } > + > trace_e1000e_irq_icr_read_exit(core->mac[ICR]); > e1000e_update_interrupt_state(core); > return ret; > diff --git a/hw/net/trace-events b/hw/net/trace-events > index e18f883cfd..46e40fcfa9 100644 > --- a/hw/net/trace-events > +++ b/hw/net/trace-events > @@ -237,6 +237,7 @@ e1000e_irq_icr_read_entry(uint32_t icr) "Starting ICR= read. Current ICR: 0x%x" > e1000e_irq_icr_read_exit(uint32_t icr) "Ending ICR read. Current ICR: 0= x%x" > e1000e_irq_icr_clear_zero_ims(void) "Clearing ICR on read due to zero I= MS" > e1000e_irq_icr_clear_iame(void) "Clearing ICR on read due to IAME" > +e1000e_irq_icr_clear_icr_bit_ims(uint32_t icr, uint32_t ims) "Clearing I= CR on read due corresponding IMS bit: 0x%x & 0x%x" > e1000e_irq_iam_clear_eiame(uint32_t iam, uint32_t cause) "Clearing IMS = due to EIAME, IAM: 0x%X, cause: 0x%X" > e1000e_irq_icr_clear_eiac(uint32_t icr, uint32_t eiac) "Clearing ICR bi= ts due to EIAC, ICR: 0x%X, EIAC: 0x%X" > e1000e_irq_ims_clear_set_imc(uint32_t val) "Clearing IMS bits due to IM= C write 0x%x"