From: "Philippe Mathieu-Daudé" <philmd@linaro.org>
To: Richard Henderson <richard.henderson@linaro.org>, qemu-devel@nongnu.org
Cc: pbonzini@redhat.com
Subject: Re: [PATCH v3 15/38] target/s390x: Improve general case of disas_jcc
Date: Tue, 16 Jan 2024 23:19:42 +0100 [thread overview]
Message-ID: <b6a05a23-9f83-4a62-9f60-1ac5234cde31@linaro.org> (raw)
In-Reply-To: <20240110224408.10444-16-richard.henderson@linaro.org>
Hi Richard,
On 10/1/24 23:43, Richard Henderson wrote:
> Avoid code duplication by handling 7 of the 14 cases
> by inverting the test for the other 7 cases.
>
> Use TCG_COND_TSTNE for cc in {1,3}.
> Use (cc - 1) <= 1 for cc in {1,2}.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
> target/s390x/tcg/translate.c | 82 +++++++++++++-----------------------
> 1 file changed, 30 insertions(+), 52 deletions(-)
>
> diff --git a/target/s390x/tcg/translate.c b/target/s390x/tcg/translate.c
> index ae4e7b27ec..168974f2e6 100644
> --- a/target/s390x/tcg/translate.c
> +++ b/target/s390x/tcg/translate.c
> @@ -885,67 +885,45 @@ static void disas_jcc(DisasContext *s, DisasCompare *c, uint32_t mask)
> case CC_OP_STATIC:
> c->is_64 = false;
> c->u.s32.a = cc_op;
> - switch (mask) {
> - case 0x8 | 0x4 | 0x2: /* cc != 3 */
> - cond = TCG_COND_NE;
> +
> + /* Fold half of the cases using bit 3 to invert. */
> + switch (mask & 8 ? mask ^ 0xf : mask) {
> + case 0x1: /* cc == 3 */
> + cond = TCG_COND_EQ;
> c->u.s32.b = tcg_constant_i32(3);
> break;
> - case 0x8 | 0x4 | 0x1: /* cc != 2 */
> - cond = TCG_COND_NE;
> - c->u.s32.b = tcg_constant_i32(2);
> - break;
> - case 0x8 | 0x2 | 0x1: /* cc != 1 */
> - cond = TCG_COND_NE;
> - c->u.s32.b = tcg_constant_i32(1);
> - break;
> - case 0x8 | 0x2: /* cc == 0 || cc == 2 => (cc & 1) == 0 */
> - cond = TCG_COND_EQ;
> - c->u.s32.a = tcg_temp_new_i32();
> - c->u.s32.b = tcg_constant_i32(0);
> - tcg_gen_andi_i32(c->u.s32.a, cc_op, 1);
> - break;
> - case 0x8 | 0x4: /* cc < 2 */
> - cond = TCG_COND_LTU;
> - c->u.s32.b = tcg_constant_i32(2);
> - break;
> - case 0x8: /* cc == 0 */
> - cond = TCG_COND_EQ;
> - c->u.s32.b = tcg_constant_i32(0);
> - break;
> - case 0x4 | 0x2 | 0x1: /* cc != 0 */
> - cond = TCG_COND_NE;
> - c->u.s32.b = tcg_constant_i32(0);
> - break;
> - case 0x4 | 0x1: /* cc == 1 || cc == 3 => (cc & 1) != 0 */
> - cond = TCG_COND_NE;
> - c->u.s32.a = tcg_temp_new_i32();
> - c->u.s32.b = tcg_constant_i32(0);
> - tcg_gen_andi_i32(c->u.s32.a, cc_op, 1);
> - break;
> - case 0x4: /* cc == 1 */
> - cond = TCG_COND_EQ;
> - c->u.s32.b = tcg_constant_i32(1);
> - break;
> - case 0x2 | 0x1: /* cc > 1 */
> - cond = TCG_COND_GTU;
> - c->u.s32.b = tcg_constant_i32(1);
> - break;
> case 0x2: /* cc == 2 */
> cond = TCG_COND_EQ;
> c->u.s32.b = tcg_constant_i32(2);
> break;
> - case 0x1: /* cc == 3 */
> + case 0x4: /* cc == 1 */
> cond = TCG_COND_EQ;
> - c->u.s32.b = tcg_constant_i32(3);
> + c->u.s32.b = tcg_constant_i32(1);
> + break;
> + case 0x2 | 0x1: /* cc == 2 || cc == 3 => cc > 1 */
> + cond = TCG_COND_GTU;
> + c->u.s32.b = tcg_constant_i32(1);
> + break;
> + case 0x4 | 0x1: /* cc == 1 || cc == 3 => (cc & 1) != 0 */
> + cond = TCG_COND_TSTNE;
> + c->u.s32.b = tcg_constant_i32(1);
Don't we need to AND?
c->u.s32.a = tcg_temp_new_i32();
tcg_gen_andi_i32(c->u.s32.a, cc_op, 1);
> + break;
> + case 0x4 | 0x2: /* cc == 1 || cc == 2 => (cc - 1) <= 1 */
> + cond = TCG_COND_LEU;
> + c->u.s32.a = tcg_temp_new_i32();
> + c->u.s32.b = tcg_constant_i32(1);
> + tcg_gen_addi_i32(c->u.s32.a, cc_op, -1);
> + break;
> + case 0x4 | 0x2 | 0x1: /* cc != 0 */
> + cond = TCG_COND_NE;
> + c->u.s32.b = tcg_constant_i32(0);
> break;
> default:
> - /* CC is masked by something else: (8 >> cc) & mask. */
> - cond = TCG_COND_NE;
> - c->u.s32.a = tcg_temp_new_i32();
> - c->u.s32.b = tcg_constant_i32(0);
> - tcg_gen_shr_i32(c->u.s32.a, tcg_constant_i32(8), cc_op);
> - tcg_gen_andi_i32(c->u.s32.a, c->u.s32.a, mask);
> - break;
> + /* case 0: never, handled above. */
> + g_assert_not_reached();
> + }
> + if (mask & 8) {
> + cond = tcg_invert_cond(cond);
> }
> break;
>
next prev parent reply other threads:[~2024-01-16 22:20 UTC|newest]
Thread overview: 70+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-01-10 22:43 [PATCH v3 00/38] tcg: Introduce TCG_COND_TST{EQ,NE} Richard Henderson
2024-01-10 22:43 ` [PATCH v3 01/38] " Richard Henderson
2024-01-10 22:43 ` [PATCH v3 02/38] tcg: Introduce TCG_TARGET_HAS_tst Richard Henderson
2024-01-16 21:42 ` Philippe Mathieu-Daudé
2024-01-10 22:43 ` [PATCH v3 03/38] tcg/optimize: Split out arg_is_const_val Richard Henderson
2024-01-10 22:43 ` [PATCH v3 04/38] tcg/optimize: Split out do_constant_folding_cond1 Richard Henderson
2024-01-10 22:43 ` [PATCH v3 05/38] tcg/optimize: Do swap_commutative2 in do_constant_folding_cond2 Richard Henderson
2024-01-10 22:43 ` [PATCH v3 06/38] tcg/optimize: Handle TCG_COND_TST{EQ,NE} Richard Henderson
2024-01-10 22:43 ` [PATCH v3 07/38] tcg/optimize: Lower TCG_COND_TST{EQ, NE} if unsupported Richard Henderson
2024-01-16 22:02 ` [PATCH v3 07/38] tcg/optimize: Lower TCG_COND_TST{EQ,NE} " Philippe Mathieu-Daudé
2024-01-10 22:43 ` [PATCH v3 08/38] target/alpha: Pass immediate value to gen_bcond_internal() Richard Henderson
2024-01-16 22:02 ` Philippe Mathieu-Daudé
2024-01-10 22:43 ` [PATCH v3 09/38] target/alpha: Use TCG_COND_TST{EQ,NE} for BLB{C,S} Richard Henderson
2024-01-16 22:03 ` Philippe Mathieu-Daudé
2024-01-10 22:43 ` [PATCH v3 10/38] target/alpha: Use TCG_COND_TST{EQ, NE} for CMOVLB{C, S} Richard Henderson
2024-01-10 22:43 ` [PATCH v3 11/38] target/alpha: Use TCG_COND_TSTNE for gen_fold_mzero Richard Henderson
2024-01-10 22:43 ` [PATCH v3 12/38] target/m68k: Use TCG_COND_TST{EQ, NE} in gen_fcc_cond Richard Henderson
2024-01-16 22:06 ` [PATCH v3 12/38] target/m68k: Use TCG_COND_TST{EQ,NE} " Philippe Mathieu-Daudé
2024-01-10 22:43 ` [PATCH v3 13/38] target/sparc: Use TCG_COND_TSTEQ in gen_op_mulscc Richard Henderson
2024-01-16 21:44 ` Philippe Mathieu-Daudé
2024-01-10 22:43 ` [PATCH v3 14/38] target/s390x: Use TCG_COND_TSTNE for CC_OP_{TM,ICM} Richard Henderson
2024-01-19 21:59 ` Philippe Mathieu-Daudé
2024-01-10 22:43 ` [PATCH v3 15/38] target/s390x: Improve general case of disas_jcc Richard Henderson
2024-01-16 22:19 ` Philippe Mathieu-Daudé [this message]
2024-01-17 3:19 ` Richard Henderson
2024-01-19 23:27 ` Philippe Mathieu-Daudé
2024-01-19 23:22 ` [PATCH v3 15/38 1/6] target/s390x: Reorder CC_OP_STATIC switch case in disas_jcc (1/5) Philippe Mathieu-Daudé
2024-01-19 23:22 ` [PATCH v3 15/38 2/6] target/s390x: Reorder CC_OP_STATIC switch case in disas_jcc (2/5) Philippe Mathieu-Daudé
2024-01-19 23:22 ` [PATCH v3 15/38 3/6] target/s390x: Reorder CC_OP_STATIC switch case in disas_jcc (3/5) Philippe Mathieu-Daudé
2024-01-19 23:23 ` [PATCH v3 15/38 4/6] target/s390x: Reorder CC_OP_STATIC switch case in disas_jcc (4/5) Philippe Mathieu-Daudé
2024-01-19 23:23 ` [PATCH v3 15/38 5/6] target/s390x: Reorder CC_OP_STATIC switch case in disas_jcc (5/5) Philippe Mathieu-Daudé
2024-01-19 23:23 ` [PATCH v3 15/38 6/6] target/s390x: Improve general case of disas_jcc Philippe Mathieu-Daudé
2024-01-19 23:27 ` Philippe Mathieu-Daudé
2024-01-22 21:38 ` Ilya Leoshkevich
2024-01-10 22:43 ` [PATCH v3 16/38] tcg: Add TCGConst argument to tcg_target_const_match Richard Henderson
2024-01-10 22:43 ` [PATCH v3 17/38] tcg/aarch64: Support TCG_COND_TST{EQ,NE} Richard Henderson
2024-01-19 22:09 ` Philippe Mathieu-Daudé
2024-01-10 22:43 ` [PATCH v3 18/38] tcg/aarch64: Generate TBZ, TBNZ Richard Henderson
2024-01-19 22:47 ` [PATCH v3 18/38 1/2] tcg/aarch64: Massage tcg_out_brcond() Philippe Mathieu-Daudé
2024-01-19 22:47 ` [PATCH v3 18/38 2/2] tcg/aarch64: Generate TBZ, TBNZ Philippe Mathieu-Daudé
2024-01-10 22:43 ` [PATCH v3 19/38] tcg/aarch64: Generate CBNZ for TSTNE of UINT32_MAX Richard Henderson
2024-01-22 14:20 ` Philippe Mathieu-Daudé
2024-01-10 22:43 ` [PATCH v3 20/38] tcg/arm: Factor tcg_out_cmp() out Richard Henderson
2024-01-16 22:22 ` Philippe Mathieu-Daudé
2024-01-10 22:43 ` [PATCH v3 21/38] tcg/arm: Support TCG_COND_TST{EQ,NE} Richard Henderson
2024-01-16 22:26 ` Philippe Mathieu-Daudé
2024-01-10 22:43 ` [PATCH v3 22/38] tcg/i386: Pass x86 condition codes to tcg_out_cmov Richard Henderson
2024-01-10 22:43 ` [PATCH v3 23/38] tcg/i386: Move tcg_cond_to_jcc[] into tcg_out_cmp Richard Henderson
2024-01-10 22:43 ` [PATCH v3 24/38] tcg/i386: Support TCG_COND_TST{EQ,NE} Richard Henderson
2024-01-10 22:43 ` [PATCH v3 25/38] tcg/i386: Improve TSTNE/TESTEQ vs powers of two Richard Henderson
2024-01-10 22:43 ` [PATCH v3 26/38] tcg/i386: Use TEST r,r to test 8/16/32 bits Richard Henderson
2024-01-20 11:02 ` Philippe Mathieu-Daudé
2024-01-10 22:43 ` [PATCH v3 27/38] tcg/sparc64: Hoist read of tcg_cond_to_rcond Richard Henderson
2024-01-10 22:43 ` [PATCH v3 28/38] tcg/sparc64: Pass TCGCond to tcg_out_cmp Richard Henderson
2024-01-10 22:43 ` [PATCH v3 29/38] tcg/sparc64: Support TCG_COND_TST{EQ,NE} Richard Henderson
2024-01-10 22:44 ` [PATCH v3 30/38] tcg/ppc: Sink tcg_to_bc usage into tcg_out_bc Richard Henderson
2024-01-10 22:44 ` [PATCH v3 31/38] tcg/ppc: Use cr0 in tcg_to_bc and tcg_to_isel Richard Henderson
2024-01-16 21:51 ` Philippe Mathieu-Daudé
2024-01-10 22:44 ` [PATCH v3 32/38] tcg/ppc: Tidy up tcg_target_const_match Richard Henderson
2024-01-10 22:44 ` [PATCH v3 33/38] tcg/ppc: Add TCG_CT_CONST_CMP Richard Henderson
2024-01-19 22:12 ` Philippe Mathieu-Daudé
2024-01-10 22:44 ` [PATCH v3 34/38] tcg/ppc: Support TCG_COND_TST{EQ,NE} Richard Henderson
2024-01-19 22:20 ` Philippe Mathieu-Daudé
2024-01-10 22:44 ` [PATCH v3 35/38] tcg/s390x: Split constraint A into J+U Richard Henderson
2024-01-16 21:55 ` Philippe Mathieu-Daudé
2024-01-10 22:44 ` [PATCH v3 36/38] tcg/s390x: Add TCG_CT_CONST_CMP Richard Henderson
2024-01-16 21:57 ` Philippe Mathieu-Daudé
2024-01-10 22:44 ` [PATCH v3 37/38] tcg/s390x: Support TCG_COND_TST{EQ,NE} Richard Henderson
2024-01-23 5:36 ` Philippe Mathieu-Daudé
2024-01-10 22:44 ` [PATCH v3 38/38] tcg/tci: " Richard Henderson
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