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From: "Cédric Le Goater" <clg@kaod.org>
To: Jamin Lin <jamin_lin@aspeedtech.com>,
	Peter Maydell <peter.maydell@linaro.org>,
	Steven Lee <steven_lee@aspeedtech.com>,
	Troy Lee <leetroy@gmail.com>,
	Andrew Jeffery <andrew@codeconstruct.com.au>,
	Joel Stanley <joel@jms.id.au>, Fabiano Rosas <farosas@suse.de>,
	Laurent Vivier <lvivier@redhat.com>,
	Paolo Bonzini <pbonzini@redhat.com>,
	"open list:ASPEED BMCs" <qemu-arm@nongnu.org>,
	"open list:All patches CC here" <qemu-devel@nongnu.org>
Cc: troy_lee@aspeedtech.com
Subject: Re: [PATCH v1 03/22] hw/misc/aspeed_hace: Improve readability and consistency in variable naming
Date: Tue, 1 Apr 2025 15:17:56 +0200	[thread overview]
Message-ID: <b6b0d7c1-4992-4ea1-ab1e-6cad29ae07c0@kaod.org> (raw)
In-Reply-To: <20250321092623.2097234-4-jamin_lin@aspeedtech.com>

On 3/21/25 10:25, Jamin Lin wrote:
> Currently, users define multiple local variables within different if-statements.
> To improve readability and maintain consistency in variable naming, rename the
> variables accordingly.
> Introduced "sg_addr" to clearly indicate the scatter-gather mode buffer address.
> 
> Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>


The change look OK. do_hash_operation() is a big routine, difficult
to read. It does stuff like :

     if (sg_mode) {
	    ...
     } else {
	    ...
     }

     if (acc_mode) {
	    ...
     } else {
	    ...
     }
     ...

I think we should also split it in multiple routines to reduce the
complexity, even if some part are redundant.

Thanks,

C.



> --->   hw/misc/aspeed_hace.c | 33 ++++++++++++++++-----------------
>   1 file changed, 16 insertions(+), 17 deletions(-)
> 
> diff --git a/hw/misc/aspeed_hace.c b/hw/misc/aspeed_hace.c
> index d8b5f048bb..4bcf6ed074 100644
> --- a/hw/misc/aspeed_hace.c
> +++ b/hw/misc/aspeed_hace.c
> @@ -145,15 +145,19 @@ static bool has_padding(AspeedHACEState *s, struct iovec *iov,
>   static void do_hash_operation(AspeedHACEState *s, int algo, bool sg_mode,
>                                 bool acc_mode)
>   {
> +    bool sg_acc_mode_final_request = false;
> +    g_autofree uint8_t *digest_buf = NULL;
>       struct iovec iov[ASPEED_HACE_MAX_SG];
> +    Error *local_err = NULL;
>       uint32_t total_msg_len;
> -    uint32_t pad_offset;
> -    g_autofree uint8_t *digest_buf = NULL;
>       size_t digest_len = 0;
> -    bool sg_acc_mode_final_request = false;
> -    int i;
> +    uint32_t sg_addr = 0;
> +    uint32_t pad_offset;
> +    uint32_t len = 0;
> +    uint32_t src = 0;
>       void *haddr;
> -    Error *local_err = NULL;
> +    hwaddr plen;
> +    int i;
>   
>       if (acc_mode && s->hash_ctx == NULL) {
>           s->hash_ctx = qcrypto_hash_new(algo, &local_err);
> @@ -166,12 +170,7 @@ static void do_hash_operation(AspeedHACEState *s, int algo, bool sg_mode,
>       }
>   
>       if (sg_mode) {
> -        uint32_t len = 0;
> -
>           for (i = 0; !(len & SG_LIST_LEN_LAST); i++) {
> -            uint32_t addr, src;
> -            hwaddr plen;
> -
>               if (i == ASPEED_HACE_MAX_SG) {
>                   qemu_log_mask(LOG_GUEST_ERROR,
>                           "aspeed_hace: guest failed to set end of sg list marker\n");
> @@ -183,12 +182,12 @@ static void do_hash_operation(AspeedHACEState *s, int algo, bool sg_mode,
>               len = address_space_ldl_le(&s->dram_as, src,
>                                          MEMTXATTRS_UNSPECIFIED, NULL);
>   
> -            addr = address_space_ldl_le(&s->dram_as, src + SG_LIST_LEN_SIZE,
> -                                        MEMTXATTRS_UNSPECIFIED, NULL);
> -            addr &= SG_LIST_ADDR_MASK;
> +            sg_addr = address_space_ldl_le(&s->dram_as, src + SG_LIST_LEN_SIZE,
> +                                           MEMTXATTRS_UNSPECIFIED, NULL);
> +            sg_addr &= SG_LIST_ADDR_MASK;
>   
>               plen = len & SG_LIST_LEN_MASK;
> -            haddr = address_space_map(&s->dram_as, addr, &plen, false,
> +            haddr = address_space_map(&s->dram_as, sg_addr, &plen, false,
>                                         MEMTXATTRS_UNSPECIFIED);
>               if (haddr == NULL) {
>                   qemu_log_mask(LOG_GUEST_ERROR,
> @@ -212,16 +211,16 @@ static void do_hash_operation(AspeedHACEState *s, int algo, bool sg_mode,
>               }
>           }
>       } else {
> -        hwaddr len = s->regs[R_HASH_SRC_LEN];
> +        plen = s->regs[R_HASH_SRC_LEN];
>   
>           haddr = address_space_map(&s->dram_as, s->regs[R_HASH_SRC],
> -                                  &len, false, MEMTXATTRS_UNSPECIFIED);
> +                                  &plen, false, MEMTXATTRS_UNSPECIFIED);
>           if (haddr == NULL) {
>               qemu_log_mask(LOG_GUEST_ERROR, "%s: qcrypto failed\n", __func__);
>               return;
>           }
>           iov[0].iov_base = haddr;
> -        iov[0].iov_len = len;
> +        iov[0].iov_len = plen;
>           i = 1;
>       }
>   



  reply	other threads:[~2025-04-01 13:19 UTC|newest]

Thread overview: 71+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-03-21  9:25 [PATCH v1 00/22] Fix incorrect hash results on AST2700 Jamin Lin via
2025-03-21  9:25 ` [PATCH v1 01/22] hw/misc/aspeed_hace: Remove unused code for better readability Jamin Lin via
2025-04-01 13:08   ` Cédric Le Goater
2025-05-05  3:28     ` Jamin Lin
2025-05-06  9:01       ` Cédric Le Goater
2025-03-21  9:25 ` [PATCH v1 02/22] hw/misc/aspeed_hace: Fix buffer overflow in has_padding function Jamin Lin via
2025-03-21  9:47   ` Jamin Lin
2025-03-22 20:52     ` Cédric Le Goater
2025-03-21  9:25 ` [PATCH v1 03/22] hw/misc/aspeed_hace: Improve readability and consistency in variable naming Jamin Lin via
2025-04-01 13:17   ` Cédric Le Goater [this message]
2025-05-09  6:57     ` Jamin Lin
2025-03-21  9:26 ` [PATCH v1 04/22] hw/misc/aspeed_hace: Update hash source address handling to 64-bit for AST2700 Jamin Lin via
2025-04-01 13:52   ` Cédric Le Goater
2025-05-09  6:49     ` Jamin Lin
2025-03-21  9:26 ` [PATCH v1 05/22] hw/misc/aspeed_hace: Introduce 64-bit digest_addr variable " Jamin Lin via
2025-04-01 13:55   ` Cédric Le Goater
2025-05-09  4:01     ` Jamin Lin
2025-03-21  9:26 ` [PATCH v1 06/22] hw/misc/aspeed_hace: Support accumulative mode for direct access mode Jamin Lin via
2025-04-01 13:57   ` Cédric Le Goater
2025-05-09  6:55     ` Jamin Lin
2025-05-10  6:12       ` Cédric Le Goater
2025-03-21  9:26 ` [PATCH v1 07/22] hw/misc/aspeed_hace: Add support for source, digest, key buffer 64 bit addresses Jamin Lin via
2025-04-01 16:19   ` Cédric Le Goater
2025-05-12  8:06     ` Jamin Lin
2025-03-21  9:26 ` [PATCH v1 08/22] hw/misc/aspeed_hace: Support DMA 64 bits dram address Jamin Lin via
2025-04-02  7:41   ` Cédric Le Goater
2025-05-09  7:04     ` Jamin Lin
2025-05-10  6:15       ` Cédric Le Goater
2025-05-12  8:41         ` Jamin Lin
2025-05-15  7:11           ` Jamin Lin
2025-05-15  7:19             ` Jamin Lin
2025-03-21  9:26 ` [PATCH v1 09/22] hw/misc/aspeed_hace: Ensure HASH_IRQ is always set to prevent firmware hang Jamin Lin via
2025-04-02  9:35   ` Cédric Le Goater
2025-05-06  5:08     ` Jamin Lin
2025-03-21  9:26 ` [PATCH v1 10/22] hw/misc/aspeed_hace:: Support setting different memory size Jamin Lin via
2025-04-02  7:46   ` Cédric Le Goater
2025-03-21  9:26 ` [PATCH v1 11/22] hw/misc/aspeed_hace: Add trace-events for better debugging Jamin Lin via
2025-04-02  7:59   ` Cédric Le Goater
2025-05-12  1:34     ` Jamin Lin
2025-03-21  9:26 ` [PATCH v1 12/22] hw/misc/aspeed_hace Support to dump plaintext and digest " Jamin Lin via
2025-04-02  8:05   ` Cédric Le Goater
2025-05-12  5:22     ` Jamin Lin
2025-03-21  9:26 ` [PATCH v1 13/22] test/qtest: Introduce a new aspeed-hace-utils.c to place common testcases Jamin Lin via
2025-04-02  8:54   ` Cédric Le Goater
2025-05-05  6:42     ` Jamin Lin
2025-03-21  9:26 ` [PATCH v1 14/22] test/qtest/hace: Adjust test address range for AST1030 due to SRAM limitations Jamin Lin via
2025-04-02  9:43   ` Cédric Le Goater
2025-05-05  3:44     ` Jamin Lin
2025-03-21  9:26 ` [PATCH v1 15/22] test/qtest/hace: Add SHA-384 test cases for ASPEED HACE model Jamin Lin via
2025-04-02  9:02   ` Cédric Le Goater
2025-05-05  6:36     ` Jamin Lin
2025-05-05  6:51       ` Jamin Lin
2025-05-06  8:59         ` Cédric Le Goater
2025-03-21  9:26 ` [PATCH v1 16/22] test/qtest/hace: Add SHA-384 tests for AST2600 Jamin Lin via
2025-04-02  9:02   ` Cédric Le Goater
2025-03-21  9:26 ` [PATCH v1 17/22] test/qtest/hace: Add tests for AST1030 Jamin Lin via
2025-04-02  9:44   ` Cédric Le Goater
2025-03-21  9:26 ` [PATCH v1 18/22] test/qtest/hace: Update source data and digest data type to 64-bit Jamin Lin via
2025-04-02  9:05   ` Cédric Le Goater
2025-05-12  7:14     ` Jamin Lin
2025-03-21  9:26 ` [PATCH v1 19/22] test/qtest/hace: Support 64-bit source and digest addresses for AST2700 Jamin Lin via
2025-04-02  9:06   ` Cédric Le Goater
2025-03-21  9:26 ` [PATCH v1 20/22] test/qtest/hace: Support to test upper 32 bits of digest and source addresses Jamin Lin via
2025-04-02  9:12   ` Cédric Le Goater
2025-03-21  9:26 ` [PATCH v1 21/22] test/qtest/hace: Support to validate 64-bit hmac key buffer addresses Jamin Lin via
2025-04-02  9:12   ` Cédric Le Goater
2025-03-21  9:26 ` [PATCH v1 22/22] test/qtest/hace: Add tests for AST2700 Jamin Lin via
2025-04-02  9:16   ` Cédric Le Goater
2025-03-21  9:39 ` [PATCH v1 00/22] Fix incorrect hash results on AST2700 Cédric Le Goater
2025-04-02  9:47 ` Cédric Le Goater
2025-04-02  9:54   ` Jamin Lin

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