From: Wilfred Mallawa <wilfred.mallawa@wdc.com>
To: "bmeng@tinylab.org" <bmeng@tinylab.org>,
Alistair Francis <Alistair.Francis@wdc.com>,
"qemu-devel@nongnu.org" <qemu-devel@nongnu.org>
Cc: "bin.meng@windriver.com" <bin.meng@windriver.com>,
"palmer@dabbelt.com" <palmer@dabbelt.com>,
"qemu-riscv@nongnu.org" <qemu-riscv@nongnu.org>
Subject: Re: [PATCH 10/15] hw/riscv: sifive_e: Fix the number of interrupt sources of PLIC
Date: Fri, 2 Dec 2022 00:05:07 +0000 [thread overview]
Message-ID: <b6b206aba88ff31eeed34ecfd3effd22ef62136b.camel@wdc.com> (raw)
In-Reply-To: <20221201140811.142123-10-bmeng@tinylab.org>
On Thu, 2022-12-01 at 22:08 +0800, Bin Meng wrote:
> Per chapter 10 in Freedom E310 manuals [1][2][3], E310 G002 and G003
> supports 52 interrupt sources while G000 supports 51 interrupt
> sources.
>
> We use the value of G002 and G003, so it is 53 (including source 0).
>
> [1] G000 manual:
> https://sifive.cdn.prismic.io/sifive/4faf3e34-4a42-4c2f-be9e-c77baa4928c7_fe310-g000-manual-v3p2.pdf
>
> [2] G002 manual:
> https://sifive.cdn.prismic.io/sifive/034760b5-ac6a-4b1c-911c-f4148bb2c4a5_fe310-g002-v1p5.pdf
>
> [3] G003 manual:
> https://sifive.cdn.prismic.io/sifive/3af39c59-6498-471e-9dab-5355a0d539eb_fe310-g003-manual.pdf
>
> Fixes: eb637edb1241 ("SiFive Freedom E Series RISC-V Machine")
> Signed-off-by: Bin Meng <bmeng@tinylab.org>
> ---
>
> include/hw/riscv/sifive_e.h | 7 ++++++-
> 1 file changed, 6 insertions(+), 1 deletion(-)
>
Reviewed-by: Wilfred Mallawa <wilfred.mallawa@wdc.com>
> diff --git a/include/hw/riscv/sifive_e.h
> b/include/hw/riscv/sifive_e.h
> index d738745925..9e58247fd8 100644
> --- a/include/hw/riscv/sifive_e.h
> +++ b/include/hw/riscv/sifive_e.h
> @@ -82,7 +82,12 @@ enum {
> };
>
> #define SIFIVE_E_PLIC_HART_CONFIG "M"
> -#define SIFIVE_E_PLIC_NUM_SOURCES 127
> +/*
> + * Freedom E310 G002 and G003 supports 52 interrupt sources while
> + * Freedom E310 G000 supports 51 interrupt sources. We use the value
> + * of G002 and G003, so it is 53 (including interrupt source 0).
> + */
> +#define SIFIVE_E_PLIC_NUM_SOURCES 53
> #define SIFIVE_E_PLIC_NUM_PRIORITIES 7
> #define SIFIVE_E_PLIC_PRIORITY_BASE 0x04
> #define SIFIVE_E_PLIC_PENDING_BASE 0x1000
next prev parent reply other threads:[~2022-12-02 0:05 UTC|newest]
Thread overview: 42+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-12-01 14:07 [PATCH 01/15] hw/riscv: Select MSI_NONBROKEN in SIFIVE_PLIC Bin Meng
2022-12-01 14:07 ` [PATCH 02/15] hw/intc: Select MSI_NONBROKEN in RISC-V AIA interrupt controllers Bin Meng
2022-12-04 22:23 ` Alistair Francis
2022-12-01 14:07 ` [PATCH 03/15] hw/riscv: Fix opentitan dependency to SIFIVE_PLIC Bin Meng
2022-12-01 23:36 ` Wilfred Mallawa
2022-12-04 22:23 ` Alistair Francis
2022-12-01 14:08 ` [PATCH 04/15] hw/riscv: Sort machines Kconfig options in alphabetical order Bin Meng
2022-12-04 22:24 ` Alistair Francis
2022-12-01 14:08 ` [PATCH 05/15] hw/riscv: spike: Remove misleading comments Bin Meng
2022-12-01 23:39 ` Wilfred Mallawa
2022-12-04 22:25 ` Alistair Francis
2022-12-01 14:08 ` [PATCH 06/15] hw/intc: sifive_plic: Drop PLICMode_H Bin Meng
2022-12-01 23:57 ` Wilfred Mallawa
2022-12-04 22:25 ` Alistair Francis
2022-12-01 14:08 ` [PATCH 07/15] hw/intc: sifive_plic: Improve robustness of the PLIC config parser Bin Meng
2022-12-07 4:21 ` Alistair Francis
2022-12-01 14:08 ` [PATCH 08/15] hw/intc: sifive_plic: Update "num-sources" property default value Bin Meng
2022-12-07 4:28 ` Alistair Francis
2022-12-01 14:08 ` [PATCH 09/15] hw/riscv: microchip_pfsoc: Fix the number of interrupt sources of PLIC Bin Meng
2022-12-02 0:03 ` Wilfred Mallawa
2022-12-07 4:30 ` Alistair Francis
2022-12-07 8:29 ` Conor Dooley
2022-12-01 14:08 ` [PATCH 10/15] hw/riscv: sifive_e: " Bin Meng
2022-12-02 0:05 ` Wilfred Mallawa [this message]
2022-12-07 4:31 ` Alistair Francis
2022-12-01 14:08 ` [PATCH 11/15] hw/riscv: sifive_u: Avoid using magic number for "riscv, ndev" Bin Meng
2022-12-02 0:06 ` Wilfred Mallawa
2022-12-07 4:33 ` Alistair Francis
2022-12-01 14:08 ` [PATCH 12/15] hw/riscv: virt: Fix the value of "riscv, ndev" in the dtb Bin Meng
2022-12-07 4:35 ` Alistair Francis
2022-12-01 14:08 ` [PATCH 13/15] hw/intc: sifive_plic: Change "priority-base" to start from interrupt source 0 Bin Meng
2022-12-07 4:36 ` Alistair Francis
2022-12-01 14:08 ` [PATCH 14/15] hw/riscv: opentitan: Drop "hartid-base" and "priority-base" initialization Bin Meng
2022-12-02 0:11 ` Wilfred Mallawa
2022-12-07 4:37 ` Alistair Francis
2022-12-07 10:11 ` Bin Meng
2022-12-01 14:08 ` [PATCH 15/15] hw/intc: sifive_plic: Fix the pending register range check Bin Meng
2022-12-02 0:27 ` Wilfred Mallawa
2022-12-05 8:21 ` Bin Meng
2022-12-05 22:05 ` Wilfred Mallawa
2022-12-07 5:08 ` Alistair Francis
2022-12-04 22:21 ` [PATCH 01/15] hw/riscv: Select MSI_NONBROKEN in SIFIVE_PLIC Alistair Francis
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=b6b206aba88ff31eeed34ecfd3effd22ef62136b.camel@wdc.com \
--to=wilfred.mallawa@wdc.com \
--cc=Alistair.Francis@wdc.com \
--cc=bin.meng@windriver.com \
--cc=bmeng@tinylab.org \
--cc=palmer@dabbelt.com \
--cc=qemu-devel@nongnu.org \
--cc=qemu-riscv@nongnu.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).