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[174.21.84.25]) by smtp.gmail.com with ESMTPSA id 72sm15330317pfv.5.2021.02.28.19.48.33 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Sun, 28 Feb 2021 19:48:34 -0800 (PST) Subject: Re: [PATCH v2 11/24] hw/arm/mps2-tz: Correct wrong interrupt numbers for DMA and SPI To: Peter Maydell , qemu-arm@nongnu.org, qemu-devel@nongnu.org References: <20210215115138.20465-1-peter.maydell@linaro.org> <20210215115138.20465-12-peter.maydell@linaro.org> From: Richard Henderson Message-ID: Date: Sun, 28 Feb 2021 19:48:32 -0800 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.7.1 MIME-Version: 1.0 In-Reply-To: <20210215115138.20465-12-peter.maydell@linaro.org> Content-Type: text/plain; charset=utf-8; format=flowed Content-Language: en-US Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=2607:f8b0:4864:20::42c; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, NICE_REPLY_A=-0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On 2/15/21 3:51 AM, Peter Maydell wrote: > On the MPS2 boards, the first 32 interrupt lines are entirely > internal to the SSE; interrupt lines for devices outside the SSE > start at 32. In the application notes that document each FPGA image, > the interrupt wiring is documented from the point of view of the CPU, > so '0' is the first of the SSE's interrupts and the devices in the > FPGA image itself are '32' and up: so the UART 0 Receive interrupt is > 32, the SPI #0 interrupt is 51, and so on. > > Within our implementation, because the external interrupts must be > connected to the EXP_IRQ[0...n] lines of the SSE object, we made the > get_sse_irq_in() function take an irqno whose values start at 0 for > the first FPGA device interrupt. In this numbering scheme the UART 0 > Receive interrupt is 0, the SPI #0 interrupt is 19, and so on. > > The result of these two different numbering schemes has been that > half of the devices were wired up to the wrong IRQs: the UART IRQs > are wired up correctly, but the DMA and SPI devices were passing > start-at-32 values to get_sse_irq_in() and so being mis-connected. > > Fix the bug by making get_sse_irq_in() take values specified with the > same scheme that the hardware manuals use, to avoid confusion. > > Signed-off-by: Peter Maydell > --- > hw/arm/mps2-tz.c | 24 +++++++++++++++++------- > 1 file changed, 17 insertions(+), 7 deletions(-) Reviewed-by: Richard Henderson r~