From: "Philippe Mathieu-Daudé" <philmd@redhat.com>
To: Richard Henderson <richard.henderson@linaro.org>, qemu-devel@nongnu.org
Cc: peter.maydell@linaro.org, alex.bennee@linaro.org
Subject: Re: [PATCH v4 37/40] target/arm: Move arm_excp_unmasked to cpu.c
Date: Tue, 3 Dec 2019 07:28:42 +0100 [thread overview]
Message-ID: <b6d1566d-f547-a822-9ca5-ab4e2c45ef7b@redhat.com> (raw)
In-Reply-To: <20191203022937.1474-38-richard.henderson@linaro.org>
On 12/3/19 3:29 AM, Richard Henderson wrote:
> This inline function has one user in cpu.c, and need not be exposed
> otherwise. Code movement only, with fixups for checkpatch.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
> ---
> target/arm/cpu.h | 111 -------------------------------------------
> target/arm/cpu.c | 119 +++++++++++++++++++++++++++++++++++++++++++++++
> 2 files changed, 119 insertions(+), 111 deletions(-)
>
> diff --git a/target/arm/cpu.h b/target/arm/cpu.h
> index 8e5aaaf415..22935e4433 100644
> --- a/target/arm/cpu.h
> +++ b/target/arm/cpu.h
> @@ -2673,117 +2673,6 @@ bool write_cpustate_to_list(ARMCPU *cpu, bool kvm_sync);
> #define ARM_CPUID_TI915T 0x54029152
> #define ARM_CPUID_TI925T 0x54029252
>
> -static inline bool arm_excp_unmasked(CPUState *cs, unsigned int excp_idx,
> - unsigned int target_el)
> -{
> - CPUARMState *env = cs->env_ptr;
> - unsigned int cur_el = arm_current_el(env);
> - bool secure = arm_is_secure(env);
> - bool pstate_unmasked;
> - int8_t unmasked = 0;
> - uint64_t hcr_el2;
> -
> - /* Don't take exceptions if they target a lower EL.
> - * This check should catch any exceptions that would not be taken but left
> - * pending.
> - */
> - if (cur_el > target_el) {
> - return false;
> - }
> -
> - hcr_el2 = arm_hcr_el2_eff(env);
> -
> - switch (excp_idx) {
> - case EXCP_FIQ:
> - pstate_unmasked = !(env->daif & PSTATE_F);
> - break;
> -
> - case EXCP_IRQ:
> - pstate_unmasked = !(env->daif & PSTATE_I);
> - break;
> -
> - case EXCP_VFIQ:
> - if (secure || !(hcr_el2 & HCR_FMO) || (hcr_el2 & HCR_TGE)) {
> - /* VFIQs are only taken when hypervized and non-secure. */
> - return false;
> - }
> - return !(env->daif & PSTATE_F);
> - case EXCP_VIRQ:
> - if (secure || !(hcr_el2 & HCR_IMO) || (hcr_el2 & HCR_TGE)) {
> - /* VIRQs are only taken when hypervized and non-secure. */
> - return false;
> - }
> - return !(env->daif & PSTATE_I);
> - default:
> - g_assert_not_reached();
> - }
> -
> - /* Use the target EL, current execution state and SCR/HCR settings to
> - * determine whether the corresponding CPSR bit is used to mask the
> - * interrupt.
> - */
> - if ((target_el > cur_el) && (target_el != 1)) {
> - /* Exceptions targeting a higher EL may not be maskable */
> - if (arm_feature(env, ARM_FEATURE_AARCH64)) {
> - /* 64-bit masking rules are simple: exceptions to EL3
> - * can't be masked, and exceptions to EL2 can only be
> - * masked from Secure state. The HCR and SCR settings
> - * don't affect the masking logic, only the interrupt routing.
> - */
> - if (target_el == 3 || !secure) {
> - unmasked = 1;
> - }
> - } else {
> - /* The old 32-bit-only environment has a more complicated
> - * masking setup. HCR and SCR bits not only affect interrupt
> - * routing but also change the behaviour of masking.
> - */
> - bool hcr, scr;
> -
> - switch (excp_idx) {
> - case EXCP_FIQ:
> - /* If FIQs are routed to EL3 or EL2 then there are cases where
> - * we override the CPSR.F in determining if the exception is
> - * masked or not. If neither of these are set then we fall back
> - * to the CPSR.F setting otherwise we further assess the state
> - * below.
> - */
> - hcr = hcr_el2 & HCR_FMO;
> - scr = (env->cp15.scr_el3 & SCR_FIQ);
> -
> - /* When EL3 is 32-bit, the SCR.FW bit controls whether the
> - * CPSR.F bit masks FIQ interrupts when taken in non-secure
> - * state. If SCR.FW is set then FIQs can be masked by CPSR.F
> - * when non-secure but only when FIQs are only routed to EL3.
> - */
> - scr = scr && !((env->cp15.scr_el3 & SCR_FW) && !hcr);
> - break;
> - case EXCP_IRQ:
> - /* When EL3 execution state is 32-bit, if HCR.IMO is set then
> - * we may override the CPSR.I masking when in non-secure state.
> - * The SCR.IRQ setting has already been taken into consideration
> - * when setting the target EL, so it does not have a further
> - * affect here.
> - */
> - hcr = hcr_el2 & HCR_IMO;
> - scr = false;
> - break;
> - default:
> - g_assert_not_reached();
> - }
> -
> - if ((scr || hcr) && !secure) {
> - unmasked = 1;
> - }
> - }
> - }
> -
> - /* The PSTATE bits only mask the interrupt if we have not overriden the
> - * ability above.
> - */
> - return unmasked || pstate_unmasked;
> -}
> -
> #define ARM_CPU_TYPE_SUFFIX "-" TYPE_ARM_CPU
> #define ARM_CPU_TYPE_NAME(name) (name ARM_CPU_TYPE_SUFFIX)
> #define CPU_RESOLVING_TYPE TYPE_ARM_CPU
> diff --git a/target/arm/cpu.c b/target/arm/cpu.c
> index 81c33221f7..a36344d4c7 100644
> --- a/target/arm/cpu.c
> +++ b/target/arm/cpu.c
> @@ -410,6 +410,125 @@ static void arm_cpu_reset(CPUState *s)
> arm_rebuild_hflags(env);
> }
>
> +static inline bool arm_excp_unmasked(CPUState *cs, unsigned int excp_idx,
> + unsigned int target_el)
> +{
> + CPUARMState *env = cs->env_ptr;
> + unsigned int cur_el = arm_current_el(env);
> + bool secure = arm_is_secure(env);
> + bool pstate_unmasked;
> + int8_t unmasked = 0;
> + uint64_t hcr_el2;
> +
> + /*
> + * Don't take exceptions if they target a lower EL.
> + * This check should catch any exceptions that would not be taken
> + * but left pending.
> + */
> + if (cur_el > target_el) {
> + return false;
> + }
> +
> + hcr_el2 = arm_hcr_el2_eff(env);
> +
> + switch (excp_idx) {
> + case EXCP_FIQ:
> + pstate_unmasked = !(env->daif & PSTATE_F);
> + break;
> +
> + case EXCP_IRQ:
> + pstate_unmasked = !(env->daif & PSTATE_I);
> + break;
> +
> + case EXCP_VFIQ:
> + if (secure || !(hcr_el2 & HCR_FMO) || (hcr_el2 & HCR_TGE)) {
> + /* VFIQs are only taken when hypervized and non-secure. */
> + return false;
> + }
> + return !(env->daif & PSTATE_F);
> + case EXCP_VIRQ:
> + if (secure || !(hcr_el2 & HCR_IMO) || (hcr_el2 & HCR_TGE)) {
> + /* VIRQs are only taken when hypervized and non-secure. */
> + return false;
> + }
> + return !(env->daif & PSTATE_I);
> + default:
> + g_assert_not_reached();
> + }
> +
> + /*
> + * Use the target EL, current execution state and SCR/HCR settings to
> + * determine whether the corresponding CPSR bit is used to mask the
> + * interrupt.
> + */
> + if ((target_el > cur_el) && (target_el != 1)) {
> + /* Exceptions targeting a higher EL may not be maskable */
> + if (arm_feature(env, ARM_FEATURE_AARCH64)) {
> + /*
> + * 64-bit masking rules are simple: exceptions to EL3
> + * can't be masked, and exceptions to EL2 can only be
> + * masked from Secure state. The HCR and SCR settings
> + * don't affect the masking logic, only the interrupt routing.
> + */
> + if (target_el == 3 || !secure) {
> + unmasked = 1;
> + }
> + } else {
> + /*
> + * The old 32-bit-only environment has a more complicated
> + * masking setup. HCR and SCR bits not only affect interrupt
> + * routing but also change the behaviour of masking.
> + */
> + bool hcr, scr;
> +
> + switch (excp_idx) {
> + case EXCP_FIQ:
> + /*
> + * If FIQs are routed to EL3 or EL2 then there are cases where
> + * we override the CPSR.F in determining if the exception is
> + * masked or not. If neither of these are set then we fall back
> + * to the CPSR.F setting otherwise we further assess the state
> + * below.
> + */
> + hcr = hcr_el2 & HCR_FMO;
> + scr = (env->cp15.scr_el3 & SCR_FIQ);
> +
> + /*
> + * When EL3 is 32-bit, the SCR.FW bit controls whether the
> + * CPSR.F bit masks FIQ interrupts when taken in non-secure
> + * state. If SCR.FW is set then FIQs can be masked by CPSR.F
> + * when non-secure but only when FIQs are only routed to EL3.
> + */
> + scr = scr && !((env->cp15.scr_el3 & SCR_FW) && !hcr);
> + break;
> + case EXCP_IRQ:
> + /*
> + * When EL3 execution state is 32-bit, if HCR.IMO is set then
> + * we may override the CPSR.I masking when in non-secure state.
> + * The SCR.IRQ setting has already been taken into consideration
> + * when setting the target EL, so it does not have a further
> + * affect here.
> + */
> + hcr = hcr_el2 & HCR_IMO;
> + scr = false;
> + break;
> + default:
> + g_assert_not_reached();
> + }
> +
> + if ((scr || hcr) && !secure) {
> + unmasked = 1;
> + }
> + }
> + }
> +
> + /*
> + * The PSTATE bits only mask the interrupt if we have not overriden the
> + * ability above.
> + */
> + return unmasked || pstate_unmasked;
> +}
> +
> bool arm_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
> {
> CPUClass *cc = CPU_GET_CLASS(cs);
>
next prev parent reply other threads:[~2019-12-03 6:32 UTC|newest]
Thread overview: 98+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-12-03 2:28 [PATCH v4 00/40] target/arm: Implement ARMv8.1-VHE Richard Henderson
2019-12-03 2:28 ` [PATCH v4 01/40] target/arm: Define isar_feature_aa64_vh Richard Henderson
2019-12-03 2:28 ` [PATCH v4 02/40] target/arm: Enable HCR_E2H for VHE Richard Henderson
2019-12-03 2:29 ` [PATCH v4 03/40] target/arm: Add CONTEXTIDR_EL2 Richard Henderson
2019-12-03 2:29 ` [PATCH v4 04/40] target/arm: Add TTBR1_EL2 Richard Henderson
2019-12-10 9:14 ` Laurent Desnogues
2019-12-03 2:29 ` [PATCH v4 05/40] target/arm: Update CNTVCT_EL0 for VHE Richard Henderson
2019-12-03 2:29 ` [PATCH v4 06/40] target/arm: Split out vae1_tlbmask, vmalle1_tlbmask Richard Henderson
2019-12-03 6:25 ` Philippe Mathieu-Daudé
2019-12-03 22:01 ` Richard Henderson
2019-12-03 2:29 ` [PATCH v4 07/40] target/arm: Simplify tlb_force_broadcast alternatives Richard Henderson
2019-12-03 2:29 ` [PATCH v4 08/40] target/arm: Rename ARMMMUIdx*_S12NSE* to ARMMMUIdx*_E10_* Richard Henderson
2019-12-04 10:38 ` Alex Bennée
2019-12-06 15:45 ` Peter Maydell
2019-12-06 18:00 ` Richard Henderson
2019-12-06 18:01 ` Peter Maydell
2019-12-03 2:29 ` [PATCH v4 09/40] target/arm: Rename ARMMMUIdx_S2NS to ARMMMUIdx_Stage2 Richard Henderson
2019-12-04 10:40 ` Alex Bennée
2019-12-06 15:46 ` Peter Maydell
2019-12-06 18:05 ` Richard Henderson
2019-12-03 2:29 ` [PATCH v4 10/40] target/arm: Rename ARMMMUIdx_S1NSE* to ARMMMUIdx_Stage1_E* Richard Henderson
2019-12-04 11:00 ` Alex Bennée
2019-12-06 15:47 ` Peter Maydell
2019-12-06 18:20 ` Richard Henderson
2019-12-03 2:29 ` [PATCH v4 11/40] target/arm: Rename ARMMMUIdx_S1SE* to ARMMMUIdx_SE* Richard Henderson
2019-12-04 11:01 ` Alex Bennée
2019-12-06 15:47 ` Peter Maydell
2019-12-03 2:29 ` [PATCH v4 12/40] target/arm: Rename ARMMMUIdx*_S1E3 to ARMMMUIdx*_SE3 Richard Henderson
2019-12-04 11:02 ` Alex Bennée
2019-12-03 2:29 ` [PATCH v4 13/40] target/arm: Rename ARMMMUIdx_S1E2 to ARMMMUIdx_E2 Richard Henderson
2019-12-04 11:03 ` Alex Bennée
2019-12-03 2:29 ` [PATCH v4 14/40] target/arm: Recover 4 bits from TBFLAGs Richard Henderson
2019-12-04 11:43 ` Alex Bennée
2019-12-04 14:27 ` Richard Henderson
2019-12-04 15:53 ` Alex Bennée
2019-12-04 16:19 ` Richard Henderson
2019-12-03 2:29 ` [PATCH v4 15/40] target/arm: Expand TBFLAG_ANY.MMUIDX to 4 bits Richard Henderson
2019-12-04 11:48 ` Alex Bennée
2019-12-03 2:29 ` [PATCH v4 16/40] target/arm: Rearrange ARMMMUIdxBit Richard Henderson
2019-12-04 11:56 ` Alex Bennée
2019-12-04 16:01 ` Philippe Mathieu-Daudé
2019-12-03 2:29 ` [PATCH v4 17/40] target/arm: Tidy ARMMMUIdx m-profile definitions Richard Henderson
2019-12-03 6:27 ` Philippe Mathieu-Daudé
2019-12-03 2:29 ` [PATCH v4 18/40] target/arm: Reorganize ARMMMUIdx Richard Henderson
2019-12-04 13:44 ` Alex Bennée
2019-12-03 2:29 ` [PATCH v4 19/40] target/arm: Add regime_has_2_ranges Richard Henderson
2019-12-04 14:16 ` Alex Bennée
2019-12-03 2:29 ` [PATCH v4 20/40] target/arm: Update arm_mmu_idx for VHE Richard Henderson
2019-12-04 14:37 ` Alex Bennée
2019-12-03 2:29 ` [PATCH v4 21/40] target/arm: Update arm_sctlr " Richard Henderson
2019-12-03 2:29 ` [PATCH v4 22/40] target/arm: Update aa64_zva_access for EL2 Richard Henderson
2019-12-04 15:01 ` Alex Bennée
2019-12-03 2:29 ` [PATCH v4 23/40] target/arm: Update ctr_el0_access " Richard Henderson
2019-12-04 16:11 ` Alex Bennée
2019-12-03 2:29 ` [PATCH v4 24/40] target/arm: Add the hypervisor virtual counter Richard Henderson
2019-12-03 2:29 ` [PATCH v4 25/40] target/arm: Update timer access for VHE Richard Henderson
2019-12-04 18:35 ` Alex Bennée
2019-12-03 2:29 ` [PATCH v4 26/40] target/arm: Update define_one_arm_cp_reg_with_opaque " Richard Henderson
2019-12-04 18:58 ` Alex Bennée
2019-12-04 19:47 ` Richard Henderson
2019-12-04 22:38 ` Alex Bennée
2019-12-05 15:09 ` Richard Henderson
2019-12-06 15:53 ` Peter Maydell
2019-12-03 2:29 ` [PATCH v4 27/40] target/arm: Add VHE system register redirection and aliasing Richard Henderson
2019-12-06 17:24 ` Peter Maydell
2019-12-06 18:36 ` Richard Henderson
2019-12-06 18:41 ` Peter Maydell
2019-12-06 18:53 ` Richard Henderson
2019-12-03 2:29 ` [PATCH v4 28/40] target/arm: Add VHE timer " Richard Henderson
2019-12-06 17:33 ` Peter Maydell
2019-12-03 2:29 ` [PATCH v4 29/40] target/arm: Flush tlb for ASID changes in EL2&0 translation regime Richard Henderson
2019-12-06 17:05 ` Peter Maydell
2020-01-28 0:04 ` Richard Henderson
2019-12-03 2:29 ` [PATCH v4 30/40] target/arm: Flush tlbs for E2&0 " Richard Henderson
2019-12-06 17:14 ` Peter Maydell
2020-01-29 17:05 ` Richard Henderson
2019-12-03 2:29 ` [PATCH v4 31/40] target/arm: Update arm_phys_excp_target_el for TGE Richard Henderson
2019-12-06 16:59 ` Peter Maydell
2019-12-03 2:29 ` [PATCH v4 32/40] target/arm: Update {fp,sve}_exception_el for VHE Richard Henderson
2019-12-06 16:50 ` [PATCH v4 32/40] target/arm: Update {fp, sve}_exception_el " Peter Maydell
2019-12-03 2:29 ` [PATCH v4 33/40] target/arm: check TGE and E2H flags for EL0 pauth traps Richard Henderson
2019-12-06 16:08 ` Peter Maydell
2019-12-03 2:29 ` [PATCH v4 34/40] target/arm: Update get_a64_user_mem_index for VHE Richard Henderson
2019-12-06 16:46 ` Peter Maydell
2019-12-03 2:29 ` [PATCH v4 35/40] target/arm: Update arm_cpu_do_interrupt_aarch64 " Richard Henderson
2019-12-06 16:03 ` Peter Maydell
2019-12-06 18:51 ` Richard Henderson
2019-12-06 19:15 ` Peter Maydell
2019-12-03 2:29 ` [PATCH v4 36/40] target/arm: Enable ARMv8.1-VHE in -cpu max Richard Henderson
2019-12-06 15:57 ` Peter Maydell
2019-12-03 2:29 ` [PATCH v4 37/40] target/arm: Move arm_excp_unmasked to cpu.c Richard Henderson
2019-12-03 6:28 ` Philippe Mathieu-Daudé [this message]
2019-12-03 2:29 ` [PATCH v4 38/40] target/arm: Pass more cpu state to arm_excp_unmasked Richard Henderson
2019-12-03 6:29 ` Philippe Mathieu-Daudé
2019-12-03 2:29 ` [PATCH v4 39/40] target/arm: Use bool for unmasked in arm_excp_unmasked Richard Henderson
2019-12-03 6:30 ` Philippe Mathieu-Daudé
2019-12-03 2:29 ` [PATCH v4 40/40] target/arm: Raise only one interrupt in arm_cpu_exec_interrupt Richard Henderson
2019-12-06 15:57 ` Peter Maydell
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