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[2.141.104.115]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4778bae816bsm67028455e9.0.2025.11.15.04.25.48 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Sat, 15 Nov 2025 04:25:49 -0800 (PST) Message-ID: Date: Sat, 15 Nov 2025 13:25:46 +0100 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2] target/i386: fix stack size when delivering real mode interrupts To: Paolo Bonzini , qemu-devel@nongnu.org References: <20251115015410.185195-1-pbonzini@redhat.com> From: Richard Henderson Content-Language: en-US In-Reply-To: <20251115015410.185195-1-pbonzini@redhat.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=2a00:1450:4864:20::333; envelope-from=richard.henderson@linaro.org; helo=mail-wm1-x333.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On 11/15/25 02:54, Paolo Bonzini wrote: > The stack can be 32-bit even in real mode, and in this case > the stack pointer must be updated in its entirety rather than > just the bottom 16 bits. The same is true of real mode IRET, > for which there was even a comment suggesting the right thing > to do. > > Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1506 > Signed-off-by: Paolo Bonzini > --- > target/i386/tcg/seg_helper.c | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) Applied, thanks. Please update https://wiki.qemu.org/ChangeLog/10.2 as appropriate. r~ > > diff --git a/target/i386/tcg/seg_helper.c b/target/i386/tcg/seg_helper.c > index 667b1c38696..227336c4ef2 100644 > --- a/target/i386/tcg/seg_helper.c > +++ b/target/i386/tcg/seg_helper.c > @@ -1161,7 +1161,7 @@ static void do_interrupt_real(CPUX86State *env, int intno, int is_int, > sa.env = env; > sa.ra = 0; > sa.sp = env->regs[R_ESP]; > - sa.sp_mask = 0xffff; > + sa.sp_mask = get_sp_mask(env->segs[R_SS].flags); > sa.ss_base = env->segs[R_SS].base; > sa.mmu_index = x86_mmu_index_pl(env, 0); > > @@ -1964,7 +1964,7 @@ void helper_iret_real(CPUX86State *env, int shift) > sa.env = env; > sa.ra = GETPC(); > sa.mmu_index = x86_mmu_index_pl(env, 0); > - sa.sp_mask = 0xffff; /* XXXX: use SS segment size? */ > + sa.sp_mask = get_sp_mask(env->segs[R_SS].flags); > sa.sp = env->regs[R_ESP]; > sa.ss_base = env->segs[R_SS].base; >