From: Richard Henderson <richard.henderson@linaro.org>
To: Max Chou <max.chou@sifive.com>,
qemu-devel@nongnu.org, qemu-riscv@nongnu.org
Cc: Palmer Dabbelt <palmer@dabbelt.com>,
Alistair Francis <alistair.francis@wdc.com>,
Weiwei Li <liwei1518@gmail.com>,
Daniel Henrique Barboza <dbarboza@ventanamicro.com>,
Liu Zhiwei <zhiwei_liu@linux.alibaba.com>
Subject: Re: [RFC PATCH v2 2/3] target/riscv: rvv: Add Zvqdotq support
Date: Wed, 3 Sep 2025 15:26:30 +0200 [thread overview]
Message-ID: <b70f4859-c520-4a00-b9c5-fd988dc6872a@linaro.org> (raw)
In-Reply-To: <20250903130125.1701363-3-max.chou@sifive.com>
On 9/3/25 15:01, Max Chou wrote:
> +#define OPMVV_VQDOTQ(NAME, TD, T1, T2, TX1, TX2, HD, HS1, HS2) \
> +static void do_##NAME(void *vd, void *vs1, void *vs2, int i) \
> +{ \
> + int idx; \
> + T1 r1; \
> + T2 r2; \
> + TX1 *r1_buf = (TX1 *)vs1 + HD(i); \
> + TX2 *r2_buf = (TX2 *)vs2 + HD(i); \
> + TD acc = ((TD *)vd)[HD(i)]; \
> + \
> + for (idx = 0; idx < 4; ++idx) { \
> + r1 = (TD)(*((T1 *)r1_buf + HS1(idx))); \
> + r2 = (TD)(*((T2 *)r2_buf + HS2(idx))); \
> + acc += r1 * r2; \
Incorrect typing or casting, take your pick.
I suggest
for (int idx = 0; idx < 4; ++idx) {
T1 r1 = ((T1 *)r1_buf)[HS1(idx)];
T2 r2 = ((T2 *)r1_buf)[HS2(idx)];
acc += (TD)r1 * (TD)r2;
}
r~
next prev parent reply other threads:[~2025-09-03 13:27 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-09-03 13:01 [RFC PATCH v2 0/3] Add Zvqdotq support Max Chou
2025-09-03 13:01 ` [RFC PATCH v2 1/3] target/riscv: Add Zvqdotq cfg property Max Chou
2025-09-03 13:01 ` [RFC PATCH v2 2/3] target/riscv: rvv: Add Zvqdotq support Max Chou
2025-09-03 13:26 ` Richard Henderson [this message]
2025-09-03 13:29 ` Richard Henderson
2025-09-03 13:43 ` Max Chou
2025-09-03 13:01 ` [RFC PATCH v2 3/3] target/riscv: Expose Zvqdotq extension as a cpu property Max Chou
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