[PATCH 00/23] ARM AArch64 Support for BSD

[PATCH 00/23] ARM AArch64 Support for BSD

[Ajeet Singh]

making sure to credit all the authors correctly

Stacey Son (18):
  Add CPU initialization function
  Added CPU loop function
  Added function to clone CPU state
  AArch64 specific CPU for bsd-user
  Managing CPU register for BSD-USER
  Add Aarch64 register handling
  Add ARM AArch64 TLS Management Prototypes for BSD-User
  Add Aarch64 sysarch() system call emulation for BSD-USER
  Add thread setup for BSD-USER
  Add thread initialization for BSD-USER
  Update ARM AArch64 VM parameter definitions for bsd-user
  Add ARM AArch64 ELF definitions for bsd-user
  Add ARM AArch64 sigcode setup function for bsd-user
  Add ARM AArch64 specific signal definitions for bsd-user
  Add ARM AArch64 signal trampoline argument setup for bsd-user
  Add get_mcontext function for ARM AArch64 in bsd-user
  Add set_mcontext function for ARM AArch64 in bsd-user
  Add get_ucontext_sigreturn function

Warner Losh (5):
  Add ability to get rval2
  Add ARM AArch64 hardware capability definitions
  Add function to retrieve ARM AArch64 hardware capabilities
  Add function to retrieve additional ARM AArch64 hwcap
  Add setup_sigframe_arch function for ARM AArch64 in bsd-user

 bsd-user/aarch64/signal.c               | 137 +++++++++++++++++
 bsd-user/aarch64/target_arch.h          |  28 ++++
 bsd-user/aarch64/target_arch_cpu.c      |  34 +++++
 bsd-user/aarch64/target_arch_cpu.h      | 191 ++++++++++++++++++++++++
 bsd-user/aarch64/target_arch_elf.h      | 165 ++++++++++++++++++++
 bsd-user/aarch64/target_arch_reg.h      |  56 +++++++
 bsd-user/aarch64/target_arch_signal.h   |  80 ++++++++++
 bsd-user/aarch64/target_arch_sigtramp.h |  48 ++++++
 bsd-user/aarch64/target_arch_sysarch.h  |  42 ++++++
 bsd-user/aarch64/target_arch_thread.h   |  61 ++++++++
 bsd-user/aarch64/target_arch_vmparam.h  |  74 +++++++++
 bsd-user/aarch64/target_syscall.h       |  51 +++++++
 12 files changed, 967 insertions(+)
 create mode 100644 bsd-user/aarch64/signal.c
 create mode 100644 bsd-user/aarch64/target_arch.h
 create mode 100644 bsd-user/aarch64/target_arch_cpu.c
 create mode 100644 bsd-user/aarch64/target_arch_cpu.h
 create mode 100644 bsd-user/aarch64/target_arch_elf.h
 create mode 100644 bsd-user/aarch64/target_arch_reg.h
 create mode 100644 bsd-user/aarch64/target_arch_signal.h
 create mode 100644 bsd-user/aarch64/target_arch_sigtramp.h
 create mode 100644 bsd-user/aarch64/target_arch_sysarch.h
 create mode 100644 bsd-user/aarch64/target_arch_thread.h
 create mode 100644 bsd-user/aarch64/target_arch_vmparam.h
 create mode 100644 bsd-user/aarch64/target_syscall.h

-- 
2.34.1

[PATCH 01/23] Add CPU initialization function

[Ajeet Singh]

From: Stacey Son <sson@FreeBSD.org>

Addded function to initialize ARM CPU
and to check if it supports 64 bit mode

Signed-off-by: Ajeet Singh <itachis@FreeBSD.org>
Signed-off-by: Stacey Son <sson@FreeBSD.org>
---
 bsd-user/aarch64/target_arch_cpu.h | 42 ++++++++++++++++++++++++++++++
 1 file changed, 42 insertions(+)
 create mode 100644 bsd-user/aarch64/target_arch_cpu.h

diff --git a/bsd-user/aarch64/target_arch_cpu.h b/bsd-user/aarch64/target_arch_cpu.h
new file mode 100644
index 0000000000..db5c7062b9
--- /dev/null
+++ b/bsd-user/aarch64/target_arch_cpu.h
@@ -0,0 +1,42 @@
+/*
+ *  ARM AArch64 cpu init and loop
+ *
+ * Copyright (c) 2015 Stacey Son
+ *
+ * This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Lesser General Public
+ * License as published by the Free Software Foundation; either
+ * version 2 of the License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with this library; if not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef TARGET_ARCH_CPU_H
+#define TARGET_ARCH_CPU_H
+
+#include "target_arch.h"
+#include "target/arm/syndrome.h"
+
+#define TARGET_DEFAULT_CPU_MODEL "any"
+
+static inline void target_cpu_init(CPUARMState *env,
+    struct target_pt_regs *regs)
+{
+    int i;
+
+    if (!(arm_feature(env, ARM_FEATURE_AARCH64))) {
+        fprintf(stderr, "The selected ARM CPU does not support 64 bit mode\n");
+        exit(1);
+    }
+    for (i = 0; i < 31; i++) {
+        env->xregs[i] = regs->regs[i];
+    }
+    env->pc = regs->pc;
+    env->xregs[31] = regs->sp;
+}
-- 
2.34.1

[PATCH 02/23] Added CPU loop function

[Ajeet Singh]

From: Stacey Son <sson@FreeBSD.org>

CPU loop function to handle exceptions
and emulate execution of instructions

Signed-off-by: Stacey Son <sson@FreeBSD.org>
Signed-off-by: Ajeet Singh <itachis@FreeBSD.org>
Co-authored-by: Kyle Evans <kevans@freebsd.org>
Co-authored-by: Sean Bruno <sbruno@freebsd.org>
Co-authored-by: Jessica Clarke <jrtc27@jrtc27.com>
---
 bsd-user/aarch64/target_arch_cpu.h | 132 +++++++++++++++++++++++++++++
 1 file changed, 132 insertions(+)

diff --git a/bsd-user/aarch64/target_arch_cpu.h b/bsd-user/aarch64/target_arch_cpu.h
index db5c7062b9..1962d2c99b 100644
--- a/bsd-user/aarch64/target_arch_cpu.h
+++ b/bsd-user/aarch64/target_arch_cpu.h
@@ -40,3 +40,135 @@ static inline void target_cpu_init(CPUARMState *env,
     env->pc = regs->pc;
     env->xregs[31] = regs->sp;
 }
+
+
+static inline void target_cpu_loop(CPUARMState *env)
+{
+    CPUState *cs = env_cpu(env);
+    int trapnr, ec, fsc, si_code, si_signo;
+    uint64_t code, arg1, arg2, arg3, arg4, arg5, arg6, arg7, arg8;
+    uint32_t pstate;
+    abi_long ret;
+
+    for (;;) {
+        cpu_exec_start(cs);
+        trapnr = cpu_exec(cs);
+        cpu_exec_end(cs);
+        process_queued_cpu_work(cs);
+
+        switch (trapnr) {
+        case EXCP_SWI:
+            /* See arm64/arm64/trap.c cpu_fetch_syscall_args() */
+            code = env->xregs[8];
+            if (code == TARGET_FREEBSD_NR_syscall ||
+                code == TARGET_FREEBSD_NR___syscall) {
+                code = env->xregs[0];
+                arg1 = env->xregs[1];
+                arg2 = env->xregs[2];
+                arg3 = env->xregs[3];
+                arg4 = env->xregs[4];
+                arg5 = env->xregs[5];
+                arg6 = env->xregs[6];
+                arg7 = env->xregs[7];
+                arg8 = 0;
+            } else {
+                arg1 = env->xregs[0];
+                arg2 = env->xregs[1];
+                arg3 = env->xregs[2];
+                arg4 = env->xregs[3];
+                arg5 = env->xregs[4];
+                arg6 = env->xregs[5];
+                arg7 = env->xregs[6];
+                arg8 = env->xregs[7];
+            }
+            ret = do_freebsd_syscall(env, code, arg1, arg2, arg3,
+                    arg4, arg5, arg6, arg7, arg8);
+            /*
+             * The carry bit is cleared for no error; set for error.
+             * See arm64/arm64/vm_machdep.c cpu_set_syscall_retval()
+             */
+            pstate = pstate_read(env);
+            if (ret >= 0) {
+                pstate &= ~PSTATE_C;
+                env->xregs[0] = ret;
+            } else if (ret == -TARGET_ERESTART) {
+                env->pc -= 4;
+                break;
+            } else if (ret != -TARGET_EJUSTRETURN) {
+                pstate |= PSTATE_C;
+                env->xregs[0] = -ret;
+            }
+            pstate_write(env, pstate);
+            break;
+
+        case EXCP_INTERRUPT:
+            /* Just indicate that signals should be handle ASAP. */
+            break;
+
+        case EXCP_UDEF:
+            force_sig_fault(TARGET_SIGILL, TARGET_ILL_ILLOPN, env->pc);
+            break;
+
+
+        case EXCP_PREFETCH_ABORT:
+        case EXCP_DATA_ABORT:
+            /* We should only arrive here with EC in {DATAABORT, INSNABORT}. */
+            ec = syn_get_ec(env->exception.syndrome);
+            assert(ec == EC_DATAABORT || ec == EC_INSNABORT);
+
+            /* Both EC have the same format for FSC, or close enough. */
+            fsc = extract32(env->exception.syndrome, 0, 6);
+            switch (fsc) {
+            case 0x04 ... 0x07: /* Translation fault, level {0-3} */
+                si_signo = TARGET_SIGSEGV;
+                si_code = TARGET_SEGV_MAPERR;
+                break;
+            case 0x09 ... 0x0b: /* Access flag fault, level {1-3} */
+            case 0x0d ... 0x0f: /* Permission fault, level {1-3} */
+                si_signo = TARGET_SIGSEGV;
+                si_code = TARGET_SEGV_ACCERR;
+                break;
+            case 0x11: /* Synchronous Tag Check Fault */
+                si_signo = TARGET_SIGSEGV;
+                si_code = /* TARGET_SEGV_MTESERR; */ TARGET_SEGV_ACCERR;
+                break;
+            case 0x21: /* Alignment fault */
+                si_signo = TARGET_SIGBUS;
+                si_code = TARGET_BUS_ADRALN;
+                break;
+            default:
+                g_assert_not_reached();
+            }
+            force_sig_fault(si_signo, si_code, env->exception.vaddress);
+            break;
+
+        case EXCP_DEBUG:
+        case EXCP_BKPT:
+            force_sig_fault(TARGET_SIGTRAP, TARGET_TRAP_BRKPT, env->pc);
+            break;
+
+        case EXCP_ATOMIC:
+            cpu_exec_step_atomic(cs);
+            break;
+
+        case EXCP_YIELD:
+            /* nothing to do here for user-mode, just resume guest code */
+            break;
+        default:
+            fprintf(stderr, "qemu: unhandled CPU exception 0x%x - aborting\n",
+                    trapnr);
+            cpu_dump_state(cs, stderr, 0);
+            abort();
+        } /* switch() */
+        process_pending_signals(env);
+        /*
+         * Exception return on AArch64 always clears the exclusive
+         * monitor, so any return to running guest code implies this.
+         * A strex (successful or otherwise) also clears the monitor, so
+         * we don't need to specialcase EXCP_STREX.
+         */
+        env->exclusive_addr = -1;
+    } /* for (;;) */
+}
+
+#endif /* TARGET_ARCH_CPU_H */
-- 
2.34.1

[PATCH 03/23] Added function to clone CPU state

[Ajeet Singh]

From: Stacey Son <sson@FreeBSD.org>

Function can copy cpu state to create new thread

Signed-off-by: Stacey Son <sson@FreeBSD.org>
Signed-off-by: Ajeet Singh <itachis@FreeBSD.org>
---
 bsd-user/aarch64/target_arch_cpu.h | 17 +++++++++++++++++
 1 file changed, 17 insertions(+)

diff --git a/bsd-user/aarch64/target_arch_cpu.h b/bsd-user/aarch64/target_arch_cpu.h
index 1962d2c99b..4e950305d3 100644
--- a/bsd-user/aarch64/target_arch_cpu.h
+++ b/bsd-user/aarch64/target_arch_cpu.h
@@ -171,4 +171,21 @@ static inline void target_cpu_loop(CPUARMState *env)
     } /* for (;;) */
 }
 
+
+/* See arm64/arm64/vm_machdep.c cpu_fork() */
+static inline void target_cpu_clone_regs(CPUARMState *env, target_ulong newsp)
+{
+    if (newsp) {
+        env->xregs[31] = newsp;
+    }
+    env->regs[0] = 0;
+    env->regs[1] = 0;
+    pstate_write(env, 0);
+}
+
+static inline void target_cpu_reset(CPUArchState *env)
+{
+}
+
+
 #endif /* TARGET_ARCH_CPU_H */
-- 
2.34.1

[PATCH 04/23] AArch64 specific CPU for bsd-user

[Ajeet Singh]

From: Stacey Son <sson@FreeBSD.org>

Function to set and recieve thread-local-storage value
from tpidr_el0 register

Signed-off-by: Stacey Son <sson@FreeBSD.org>
Signed-off-by: Ajeet Singh <itachis@FreeBSD.org>
---
 bsd-user/aarch64/target_arch_cpu.c | 34 ++++++++++++++++++++++++++++++
 1 file changed, 34 insertions(+)
 create mode 100644 bsd-user/aarch64/target_arch_cpu.c

diff --git a/bsd-user/aarch64/target_arch_cpu.c b/bsd-user/aarch64/target_arch_cpu.c
new file mode 100644
index 0000000000..70ef651827
--- /dev/null
+++ b/bsd-user/aarch64/target_arch_cpu.c
@@ -0,0 +1,34 @@
+/*
+ * ARM AArch64 specific CPU for bsd-user
+ *
+ * Copyright (c) 2015 Stacey Son
+ *
+ * This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Lesser General Public
+ * License as published by the Free Software Foundation; either
+ * version 2 of the License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with this library; if not, see <http://www.gnu.org/licenses/>.
+ */
+#include "qemu/osdep.h"
+
+#include "target_arch.h"
+
+/* See cpu_set_user_tls() in arm64/arm64/vm_machdep.c */
+void target_cpu_set_tls(CPUARMState *env, target_ulong newtls)
+{
+
+    env->cp15.tpidr_el[0] = newtls;
+}
+
+target_ulong target_cpu_get_tls(CPUARMState *env)
+{
+
+    return env->cp15.tpidr_el[0];
+}
-- 
2.34.1

[PATCH 05/23] Managing CPU register for BSD-USER

[Ajeet Singh]

From: Stacey Son <sson@FreeBSD.org>

Added structure for storing register states

Signed-off-by: Stacey Son <sson@FreeBSD.org>
Signed-off-by: Ajeet Singh <itachis@FreeBSD.org>
Co-authored-by: Sean Bruno <sbruno@freebsd.org>
---
 bsd-user/aarch64/target_syscall.h | 51 +++++++++++++++++++++++++++++++
 1 file changed, 51 insertions(+)
 create mode 100644 bsd-user/aarch64/target_syscall.h

diff --git a/bsd-user/aarch64/target_syscall.h b/bsd-user/aarch64/target_syscall.h
new file mode 100644
index 0000000000..08ae913c42
--- /dev/null
+++ b/bsd-user/aarch64/target_syscall.h
@@ -0,0 +1,51 @@
+/*
+ * ARM AArch64 specific CPU for bsd-user
+ *
+ * Copyright (c) 2015 Stacey D. Son <sson at Freebsd>
+ *
+ * This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Lesser General Public
+ * License as published by the Free Software Foundation; either
+ * version 2 of the License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with this library; if not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef BSD_USER_AARCH64_TARGET_SYSCALL_H
+#define BSD_USER_AARCH64_TARGET_SYSCALL_H
+
+/*
+ * The aarch64 registers are named:
+ *
+ * x0 through x30 - for 64-bit-wide access (same registers)
+ * Register '31' is one of two registers depending on the instruction context:
+ *  For instructions dealing with the stack, it is the stack pointer, named rsp
+ *  For all other instructions, it is a "zero" register, which returns 0 when
+ *  read and discards data when written - named rzr (xzr, wzr)
+ *
+ * Usage during syscall/function call:
+ * r0-r7 are used for arguments and return values
+ * For syscalls, the syscall number is in r8
+ * r9-r15 are for temporary values (may get trampled)
+ * r16-r18 are used for intra-procedure-call and platform values (avoid)
+ * The called routine is expected to preserve r19-r28
+ * r29 and r30 are used as the frame register and link register (avoid)
+ * See the ARM Procedure Call Reference for details.
+ */
+struct target_pt_regs {
+    uint64_t    regs[31];
+    uint64_t    sp;
+    uint64_t    pc;
+    uint64_t    pstate;
+};
+
+#define TARGET_HW_MACHINE       "arm64"
+#define TARGET_HW_MACHINE_ARCH  "aarch64"
+
+#endif /* BSD_USER_AARCH64_TARGET_SYSCALL_H */
-- 
2.34.1

[PATCH 06/23] Add Aarch64 register handling

[Ajeet Singh]

From: Stacey Son <sson@FreeBSD.org>

Header file for managing CPU register states in
FreeBSD user mode

Signed-off-by: Stacey Son <sson@FreeBSD.org>
Signed-off-by: Ajeet Singh <itachis@FreeBSD.org>
---
 bsd-user/aarch64/target_arch_reg.h | 56 ++++++++++++++++++++++++++++++
 1 file changed, 56 insertions(+)
 create mode 100644 bsd-user/aarch64/target_arch_reg.h

diff --git a/bsd-user/aarch64/target_arch_reg.h b/bsd-user/aarch64/target_arch_reg.h
new file mode 100644
index 0000000000..5c7154f0c1
--- /dev/null
+++ b/bsd-user/aarch64/target_arch_reg.h
@@ -0,0 +1,56 @@
+/*
+ *  FreeBSD arm64 register structures
+ *
+ *  Copyright (c) 2015 Stacey Son
+ *  All rights reserved.
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; either version 2 of the License, or
+ *  (at your option) any later version.
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License
+ *  along with this program; if not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef TARGET_ARCH_REG_H
+#define TARGET_ARCH_REG_H
+
+/* See sys/arm64/include/reg.h */
+typedef struct target_reg {
+    uint64_t        x[30];
+    uint64_t        lr;
+    uint64_t        sp;
+    uint64_t        elr;
+    uint64_t        spsr;
+} target_reg_t;
+
+typedef struct target_fpreg {
+    __uint128_t     fp_q[32];
+    uint32_t        fp_sr;
+    uint32_t        fp_cr;
+} target_fpreg_t;
+
+#define tswapreg(ptr)   tswapal(ptr)
+
+static inline void target_copy_regs(target_reg_t *regs, CPUARMState *env)
+{
+    int i;
+
+    for (i = 0; i < 30; i++) {
+        regs->x[i] = tswapreg(env->xregs[i]);
+    }
+    regs->lr = tswapreg(env->xregs[30]);
+    regs->sp = tswapreg(env->xregs[31]);
+    regs->elr = tswapreg(env->pc);
+    regs->spsr = tswapreg(pstate_read(env));
+}
+
+#undef tswapreg
+
+#endif /* TARGET_ARCH_REG_H */
-- 
2.34.1

[PATCH 07/23] Add ARM AArch64 TLS Management Prototypes for BSD-User

[Ajeet Singh]

From: Stacey Son <sson@FreeBSD.org>

Prototypes for setting and getting TLS( thread local storage)

Signed-off-by: Stacey Son <sson@FreeBSD.org>
Signed-off-by: Ajeet Singh <itachis@FreeBSD.org>
---
 bsd-user/aarch64/target_arch.h | 28 ++++++++++++++++++++++++++++
 1 file changed, 28 insertions(+)
 create mode 100644 bsd-user/aarch64/target_arch.h

diff --git a/bsd-user/aarch64/target_arch.h b/bsd-user/aarch64/target_arch.h
new file mode 100644
index 0000000000..27f47de8eb
--- /dev/null
+++ b/bsd-user/aarch64/target_arch.h
@@ -0,0 +1,28 @@
+/*
+ * ARM AArch64 specific prototypes for bsd-user
+ *
+ * Copyright (c) 2015 Stacey D. Son <sson at FreeBSD>
+ *
+ * This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Lesser General Public
+ * License as published by the Free Software Foundation; either
+ * version 2 of the License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with this library; if not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef TARGET_ARCH_H
+#define TARGET_ARCH_H
+
+#include "qemu.h"
+
+void target_cpu_set_tls(CPUARMState *env, target_ulong newtls);
+target_ulong target_cpu_get_tls(CPUARMState *env);
+
+#endif /* TARGET_ARCH_H */
-- 
2.34.1

[PATCH 08/23] Add Aarch64 sysarch() system call emulation for BSD-USER

[Ajeet Singh]

From: Stacey Son <sson@FreeBSD.org>

Initial implementation of sysarch() syscall and a printing function

Signed-off-by: Stacey Son <sson@FreeBSD.org>
Signed-off-by: Ajeet Singh <itachis@FreeBSD.org>
---
 bsd-user/aarch64/target_arch_sysarch.h | 42 ++++++++++++++++++++++++++
 1 file changed, 42 insertions(+)
 create mode 100644 bsd-user/aarch64/target_arch_sysarch.h

diff --git a/bsd-user/aarch64/target_arch_sysarch.h b/bsd-user/aarch64/target_arch_sysarch.h
new file mode 100644
index 0000000000..b003015daf
--- /dev/null
+++ b/bsd-user/aarch64/target_arch_sysarch.h
@@ -0,0 +1,42 @@
+/*
+ * ARM AArch64 sysarch() system call emulation for bsd-user.
+ *
+ * Copyright (c) 2015 <sson at FreeBSD>
+ *
+ * This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Lesser General Public
+ * License as published by the Free Software Foundation; either
+ * version 2 of the License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with this library; if not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef TARGET_ARCH_SYSARCH_H
+#define TARGET_ARCH_SYSARCH_H
+
+#include "target_syscall.h"
+#include "target_arch.h"
+
+/* See sysarch() in sys/arm64/arm64/sys_machdep.c */
+static inline abi_long do_freebsd_arch_sysarch(CPUARMState *env, int op,
+        abi_ulong parms)
+{
+    int ret = -TARGET_EOPNOTSUPP;
+
+    fprintf(stderr, "sysarch");
+    return ret;
+}
+
+static inline void do_freebsd_arch_print_sysarch(
+        const struct syscallname *name, abi_long arg1, abi_long arg2,
+        abi_long arg3, abi_long arg4, abi_long arg5, abi_long arg6)
+{
+}
+
+#endif /* TARGET_ARCH_SYSARCH_H */
-- 
2.34.1

[PATCH 09/23] Add thread setup for BSD-USER

[Ajeet Singh]

From: Stacey Son <sson@FreeBSD.org>

Function for setting up thread upcall which will
add thread support to BSD-User

Signed-off-by: Stacey Son <sson@FreeBSD.org>
Signed-off-by: Ajeet Singh <itachis@FreeBSD.org>
Co-authored-by: Jessica Clarke <jrtc27@jrtc27.com>
---
 bsd-user/aarch64/target_arch_thread.h | 45 +++++++++++++++++++++++++++
 1 file changed, 45 insertions(+)
 create mode 100644 bsd-user/aarch64/target_arch_thread.h

diff --git a/bsd-user/aarch64/target_arch_thread.h b/bsd-user/aarch64/target_arch_thread.h
new file mode 100644
index 0000000000..d2f2dea7ce
--- /dev/null
+++ b/bsd-user/aarch64/target_arch_thread.h
@@ -0,0 +1,45 @@
+/*
+ * ARM AArch64 thread support for bsd-user.
+ *
+ * Copyright (c) 2015 Stacey D. Son <sson at FreeBSD>
+ *
+ * This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Lesser General Public
+ * License as published by the Free Software Foundation; either
+ * version 2 of the License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with this library; if not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef TARGET_ARCH_THREAD_H
+#define TARGET_ARCH_THREAD_H
+
+/* Compare to arm64/arm64/vm_machdep.c cpu_set_upcall_kse() */
+static inline void target_thread_set_upcall(CPUARMState *regs, abi_ulong entry,
+    abi_ulong arg, abi_ulong stack_base, abi_ulong stack_size)
+{
+    abi_ulong sp;
+
+    /*
+     * Make sure the stack is properly aligned.
+     * arm64/include/param.h (STACKLIGN() macro)
+     */
+    sp = (abi_ulong)(stack_base + stack_size) & ~(16 - 1);
+
+    /* sp = stack base */
+    regs->xregs[31] = sp;
+    /* pc = start function entry */
+    regs->pc = entry;
+    /* r0 = arg */
+    regs->xregs[0] = arg;
+
+    pstate_write(regs, PSTATE_MODE_EL0t);
+}
+
+#endif /* TARGET_ARCH_THREAD_H */
-- 
2.34.1

[PATCH 10/23] Add thread initialization for BSD-USER

[Ajeet Singh]

From: Stacey Son <sson@FreeBSD.org>

Initializes thread's register state

Signed-off-by: Stacey Son <sson@FreeBSD.org>
Signed-off-by: Ajeet Singh <itachis@FreeBSD.org>
Co-authored-by: Jessica Clarke <jrtc27@jrtc27.com>
---
 bsd-user/aarch64/target_arch_thread.h | 16 ++++++++++++++++
 1 file changed, 16 insertions(+)

diff --git a/bsd-user/aarch64/target_arch_thread.h b/bsd-user/aarch64/target_arch_thread.h
index d2f2dea7ce..bfc9050cb1 100644
--- a/bsd-user/aarch64/target_arch_thread.h
+++ b/bsd-user/aarch64/target_arch_thread.h
@@ -42,4 +42,20 @@ static inline void target_thread_set_upcall(CPUARMState *regs, abi_ulong entry,
     pstate_write(regs, PSTATE_MODE_EL0t);
 }
 
+static inline void target_thread_init(struct target_pt_regs *regs,
+        struct image_info *infop)
+{
+    abi_long stack = infop->start_stack;
+
+    /*
+     * Make sure the stack is properly aligned.
+     * arm64/include/param.h (STACKLIGN() macro)
+     */
+
+    memset(regs, 0, sizeof(*regs));
+    regs->regs[0] = infop->start_stack;
+    regs->pc = infop->entry;
+    regs->sp = stack & ~(16 - 1);
+}
+
 #endif /* TARGET_ARCH_THREAD_H */
-- 
2.34.1

[PATCH 11/23] Update ARM AArch64 VM parameter definitions for bsd-user

[Ajeet Singh]

From: Stacey Son <sson@FreeBSD.org>

Defined address spaces for FreeBSD/arm64 and added function for
getting stack pointer from CPU and setting a return value.

Signed-off-by: Stacey Son <sson@FreeBSD.org>
Signed-off-by: Warner Losh <imp@bsdimp.com>
Signed-off-by: Ajeet Singh <itachis@FreeBSD.org>
Co-authored-by: Sean Bruno <sbruno@freebsd.org>
Co-authored-by: Warner Losh <imp@bsdimp.com>
---
 bsd-user/aarch64/target_arch_vmparam.h | 68 ++++++++++++++++++++++++++
 1 file changed, 68 insertions(+)
 create mode 100644 bsd-user/aarch64/target_arch_vmparam.h

diff --git a/bsd-user/aarch64/target_arch_vmparam.h b/bsd-user/aarch64/target_arch_vmparam.h
new file mode 100644
index 0000000000..dc66e1289b
--- /dev/null
+++ b/bsd-user/aarch64/target_arch_vmparam.h
@@ -0,0 +1,68 @@
+/*
+ * ARM AArch64 VM parameters definitions for bsd-user.
+ *
+ * Copyright (c) 2015 Stacey D. Son <sson at FreeBSD>
+ *
+ * This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Lesser General Public
+ * License as published by the Free Software Foundation; either
+ * version 2 of the License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with this library; if not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef TARGET_ARCH_VMPARAM_H
+#define TARGET_ARCH_VMPARAM_H
+
+#include "cpu.h"
+
+/**
+ * FreeBSD/arm64 Address space layout.
+ *
+ * ARMv8 implements up to a 48 bit virtual address space. The address space is
+ * split into 2 regions at each end of the 64 bit address space, with an
+ * out of range "hole" in the middle.
+ *
+ * We limit the size of the two spaces to 39 bits each.
+ *
+ * Upper region:        0xffffffffffffffff
+ *                      0xffffff8000000000
+ *
+ * Hole:                0xffffff7fffffffff
+ *                      0x0000008000000000
+ *
+ * Lower region:        0x0000007fffffffff
+ *                      0x0000000000000000
+ *
+ * The upper region for the kernel, and the lower region for userland.
+ */
+
+
+/* compare to sys/arm64/include/vmparam.h */
+#define TARGET_MAXTSIZ      (1 * GiB)           /* max text size */
+#define TARGET_DFLDSIZ      (128 * MiB)         /* initial data size limit */
+#define TARGET_MAXDSIZ      (1 * GiB)           /* max data size */
+#define TARGET_DFLSSIZ      (128 * MiB)         /* initial stack size limit */
+#define TARGET_MAXSSIZ      (1 * GiB)           /* max stack size */
+#define TARGET_SGROWSIZ     (128 * KiB)         /* amount to grow stack */
+
+                /* KERNBASE - 512 MB */
+#define TARGET_VM_MAXUSER_ADDRESS   (0x00007fffff000000ULL - (512 * MiB))
+#define TARGET_USRSTACK             TARGET_VM_MAXUSER_ADDRESS
+
+static inline abi_ulong get_sp_from_cpustate(CPUARMState *state)
+{
+    return state->xregs[31]; /* sp */
+}
+
+static inline void set_second_rval(CPUARMState *state, abi_ulong retval2)
+{
+    state->xregs[1] = retval2; /* XXX not really used on 64-bit arch */
+}
+#endif /* TARGET_ARCH_VMPARAM_H */
-- 
2.34.1

[PATCH 12/23] Add ability to get rval2

[Ajeet Singh]

From: Warner Losh <imp@bsdimp.com>

Function accesses the x1 register which holds the value

Signed-off-by: Warner Losh <imp@bsdimp.com>
Signed-off-by: Ajeet Singh <itachis@FreeBSD.org>
---
 bsd-user/aarch64/target_arch_vmparam.h | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/bsd-user/aarch64/target_arch_vmparam.h b/bsd-user/aarch64/target_arch_vmparam.h
index dc66e1289b..0c35491970 100644
--- a/bsd-user/aarch64/target_arch_vmparam.h
+++ b/bsd-user/aarch64/target_arch_vmparam.h
@@ -65,4 +65,10 @@ static inline void set_second_rval(CPUARMState *state, abi_ulong retval2)
 {
     state->xregs[1] = retval2; /* XXX not really used on 64-bit arch */
 }
+
+static inline abi_ulong get_second_rval(CPUARMState *state)
+{
+    return state->xregs[1];
+}
+
 #endif /* TARGET_ARCH_VMPARAM_H */
-- 
2.34.1

[PATCH 13/23] Add ARM AArch64 ELF definitions for bsd-user

[Ajeet Singh]

From: Stacey Son <sson@FreeBSD.org>

Defined mmap and dynamic load adresses and
set various elf parameters

Signed-off-by: Stacey Son <sson@FreeBSD.org>
Signed-off-by: Ajeet Singh <itachis@FreeBSD.org>
Co-authored-by: Kyle Evans <kevans@FreeBSD.org>
---
 bsd-user/aarch64/target_arch_elf.h | 37 ++++++++++++++++++++++++++++++
 1 file changed, 37 insertions(+)
 create mode 100644 bsd-user/aarch64/target_arch_elf.h

diff --git a/bsd-user/aarch64/target_arch_elf.h b/bsd-user/aarch64/target_arch_elf.h
new file mode 100644
index 0000000000..6d0fa3525f
--- /dev/null
+++ b/bsd-user/aarch64/target_arch_elf.h
@@ -0,0 +1,37 @@
+/*
+ * ARM AArch64 ELF definitions for bsd-user
+ *
+ * Copyright (c) 2015 Stacey D. Son
+ *
+ * This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Lesser General Public
+ * License as published by the Free Software Foundation; either
+ * version 2 of the License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with this library; if not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef TARGET_ARCH_ELF_H
+#define TARGET_ARCH_ELF_H
+
+#include "target/arm/cpu-features.h"
+
+#define ELF_START_MMAP 0x80000000
+#define ELF_ET_DYN_LOAD_ADDR    0x100000
+
+#define elf_check_arch(x) ((x) == EM_AARCH64)
+
+#define ELF_CLASS       ELFCLASS64
+#define ELF_DATA        ELFDATA2LSB
+#define ELF_ARCH        EM_AARCH64
+
+#define USE_ELF_CORE_DUMP
+#define ELF_EXEC_PAGESIZE       4096
+
+#endif /* TARGET_ARCH_ELF_H */
-- 
2.34.1

[PATCH 14/23] Add ARM AArch64 hardware capability definitions

[Ajeet Singh]

From: Warner Losh <imp@bsdimp.com>

Defined a huge list of hardware capabilites and added
macros for retrieving hwcap flags

Signed-off-by: Warner Losh <imp@bsdimp.com>
Signed-off-by: Ajeet Singh <itachis@FreeBSD.org>
---
 bsd-user/aarch64/target_arch_elf.h | 61 ++++++++++++++++++++++++++++++
 1 file changed, 61 insertions(+)

diff --git a/bsd-user/aarch64/target_arch_elf.h b/bsd-user/aarch64/target_arch_elf.h
index 6d0fa3525f..41afa5a9da 100644
--- a/bsd-user/aarch64/target_arch_elf.h
+++ b/bsd-user/aarch64/target_arch_elf.h
@@ -34,4 +34,65 @@
 #define USE_ELF_CORE_DUMP
 #define ELF_EXEC_PAGESIZE       4096
 
+enum {
+    ARM_HWCAP_A64_FP            = 1 << 0,
+    ARM_HWCAP_A64_ASIMD         = 1 << 1,
+    ARM_HWCAP_A64_EVTSTRM       = 1 << 2,
+    ARM_HWCAP_A64_AES           = 1 << 3,
+    ARM_HWCAP_A64_PMULL         = 1 << 4,
+    ARM_HWCAP_A64_SHA1          = 1 << 5,
+    ARM_HWCAP_A64_SHA2          = 1 << 6,
+    ARM_HWCAP_A64_CRC32         = 1 << 7,
+    ARM_HWCAP_A64_ATOMICS       = 1 << 8,
+    ARM_HWCAP_A64_FPHP          = 1 << 9,
+    ARM_HWCAP_A64_ASIMDHP       = 1 << 10,
+    ARM_HWCAP_A64_CPUID         = 1 << 11,
+    ARM_HWCAP_A64_ASIMDRDM      = 1 << 12,
+    ARM_HWCAP_A64_JSCVT         = 1 << 13,
+    ARM_HWCAP_A64_FCMA          = 1 << 14,
+    ARM_HWCAP_A64_LRCPC         = 1 << 15,
+    ARM_HWCAP_A64_DCPOP         = 1 << 16,
+    ARM_HWCAP_A64_SHA3          = 1 << 17,
+    ARM_HWCAP_A64_SM3           = 1 << 18,
+    ARM_HWCAP_A64_SM4           = 1 << 19,
+    ARM_HWCAP_A64_ASIMDDP       = 1 << 20,
+    ARM_HWCAP_A64_SHA512        = 1 << 21,
+    ARM_HWCAP_A64_SVE           = 1 << 22,
+    ARM_HWCAP_A64_ASIMDFHM      = 1 << 23,
+    ARM_HWCAP_A64_DIT           = 1 << 24,
+    ARM_HWCAP_A64_USCAT         = 1 << 25,
+    ARM_HWCAP_A64_ILRCPC        = 1 << 26,
+    ARM_HWCAP_A64_FLAGM         = 1 << 27,
+    ARM_HWCAP_A64_SSBS          = 1 << 28,
+    ARM_HWCAP_A64_SB            = 1 << 29,
+    ARM_HWCAP_A64_PACA          = 1 << 30,
+    ARM_HWCAP_A64_PACG          = 1UL << 31,
+
+    ARM_HWCAP2_A64_DCPODP       = 1 << 0,
+    ARM_HWCAP2_A64_SVE2         = 1 << 1,
+    ARM_HWCAP2_A64_SVEAES       = 1 << 2,
+    ARM_HWCAP2_A64_SVEPMULL     = 1 << 3,
+    ARM_HWCAP2_A64_SVEBITPERM   = 1 << 4,
+    ARM_HWCAP2_A64_SVESHA3      = 1 << 5,
+    ARM_HWCAP2_A64_SVESM4       = 1 << 6,
+    ARM_HWCAP2_A64_FLAGM2       = 1 << 7,
+    ARM_HWCAP2_A64_FRINT        = 1 << 8,
+    ARM_HWCAP2_A64_SVEI8MM      = 1 << 9,
+    ARM_HWCAP2_A64_SVEF32MM     = 1 << 10,
+    ARM_HWCAP2_A64_SVEF64MM     = 1 << 11,
+    ARM_HWCAP2_A64_SVEBF16      = 1 << 12,
+    ARM_HWCAP2_A64_I8MM         = 1 << 13,
+    ARM_HWCAP2_A64_BF16         = 1 << 14,
+    ARM_HWCAP2_A64_DGH          = 1 << 15,
+    ARM_HWCAP2_A64_RNG          = 1 << 16,
+    ARM_HWCAP2_A64_BTI          = 1 << 17,
+    ARM_HWCAP2_A64_MTE          = 1 << 18,
+};
+
+#define ELF_HWCAP   get_elf_hwcap()
+#define ELF_HWCAP2  get_elf_hwcap2()
+
+#define GET_FEATURE_ID(feat, hwcap) \
+    do { if (cpu_isar_feature(feat, cpu)) { hwcaps |= hwcap; } } while (0)
+
 #endif /* TARGET_ARCH_ELF_H */
-- 
2.34.1

[PATCH 15/23] Add function to retrieve ARM AArch64 hardware capabilities

[Ajeet Singh]

From: Warner Losh <imp@bsdimp.com>

The function initializes default hardware capabilities and
finds additional features using the `GET_FEATURE_ID` macro

Signed-off-by: Warner Losh <imp@bsdimp.com>
Signed-off-by: Ajeet Singh <itachis@FreeBSD.org>
---
 bsd-user/aarch64/target_arch_elf.h | 38 ++++++++++++++++++++++++++++++
 1 file changed, 38 insertions(+)

diff --git a/bsd-user/aarch64/target_arch_elf.h b/bsd-user/aarch64/target_arch_elf.h
index 41afa5a9da..ed2419408e 100644
--- a/bsd-user/aarch64/target_arch_elf.h
+++ b/bsd-user/aarch64/target_arch_elf.h
@@ -95,4 +95,42 @@ enum {
 #define GET_FEATURE_ID(feat, hwcap) \
     do { if (cpu_isar_feature(feat, cpu)) { hwcaps |= hwcap; } } while (0)
 
+static uint32_t get_elf_hwcap(void)
+{
+    ARMCPU *cpu = ARM_CPU(thread_cpu);
+    uint32_t hwcaps = 0;
+
+    hwcaps |= ARM_HWCAP_A64_FP;
+    hwcaps |= ARM_HWCAP_A64_ASIMD;
+    hwcaps |= ARM_HWCAP_A64_CPUID;
+
+    /* probe for the extra features */
+
+    GET_FEATURE_ID(aa64_aes, ARM_HWCAP_A64_AES);
+    GET_FEATURE_ID(aa64_pmull, ARM_HWCAP_A64_PMULL);
+    GET_FEATURE_ID(aa64_sha1, ARM_HWCAP_A64_SHA1);
+    GET_FEATURE_ID(aa64_sha256, ARM_HWCAP_A64_SHA2);
+    GET_FEATURE_ID(aa64_sha512, ARM_HWCAP_A64_SHA512);
+    GET_FEATURE_ID(aa64_crc32, ARM_HWCAP_A64_CRC32);
+    GET_FEATURE_ID(aa64_sha3, ARM_HWCAP_A64_SHA3);
+    GET_FEATURE_ID(aa64_sm3, ARM_HWCAP_A64_SM3);
+    GET_FEATURE_ID(aa64_sm4, ARM_HWCAP_A64_SM4);
+    GET_FEATURE_ID(aa64_fp16, ARM_HWCAP_A64_FPHP | ARM_HWCAP_A64_ASIMDHP);
+    GET_FEATURE_ID(aa64_atomics, ARM_HWCAP_A64_ATOMICS);
+    GET_FEATURE_ID(aa64_rdm, ARM_HWCAP_A64_ASIMDRDM);
+    GET_FEATURE_ID(aa64_dp, ARM_HWCAP_A64_ASIMDDP);
+    GET_FEATURE_ID(aa64_fcma, ARM_HWCAP_A64_FCMA);
+    GET_FEATURE_ID(aa64_sve, ARM_HWCAP_A64_SVE);
+    GET_FEATURE_ID(aa64_pauth, ARM_HWCAP_A64_PACA | ARM_HWCAP_A64_PACG);
+    GET_FEATURE_ID(aa64_fhm, ARM_HWCAP_A64_ASIMDFHM);
+    GET_FEATURE_ID(aa64_jscvt, ARM_HWCAP_A64_JSCVT);
+    GET_FEATURE_ID(aa64_sb, ARM_HWCAP_A64_SB);
+    GET_FEATURE_ID(aa64_condm_4, ARM_HWCAP_A64_FLAGM);
+    GET_FEATURE_ID(aa64_dcpop, ARM_HWCAP_A64_DCPOP);
+    GET_FEATURE_ID(aa64_rcpc_8_3, ARM_HWCAP_A64_LRCPC);
+    GET_FEATURE_ID(aa64_rcpc_8_4, ARM_HWCAP_A64_ILRCPC);
+
+    return hwcaps;
+}
+
 #endif /* TARGET_ARCH_ELF_H */
-- 
2.34.1

[PATCH 16/23] Add function to retrieve additional ARM AArch64 hwcap

[Ajeet Singh]

From: Warner Losh <imp@bsdimp.com>

Function to retrieve the extended hardware capability flags

Signed-off-by: Warner Losh <imp@bsdimp.com>
Signed-off-by: Ajeet Singh <itachis@FreeBSD.org>
---
 bsd-user/aarch64/target_arch_elf.h | 29 +++++++++++++++++++++++++++++
 1 file changed, 29 insertions(+)

diff --git a/bsd-user/aarch64/target_arch_elf.h b/bsd-user/aarch64/target_arch_elf.h
index ed2419408e..7202cd8334 100644
--- a/bsd-user/aarch64/target_arch_elf.h
+++ b/bsd-user/aarch64/target_arch_elf.h
@@ -133,4 +133,33 @@ static uint32_t get_elf_hwcap(void)
     return hwcaps;
 }
 
+static uint32_t get_elf_hwcap2(void)
+{
+    ARMCPU *cpu = ARM_CPU(thread_cpu);
+    uint32_t hwcaps = 0;
+
+    GET_FEATURE_ID(aa64_dcpodp, ARM_HWCAP2_A64_DCPODP);
+    GET_FEATURE_ID(aa64_sve2, ARM_HWCAP2_A64_SVE2);
+    GET_FEATURE_ID(aa64_sve2_aes, ARM_HWCAP2_A64_SVEAES);
+    GET_FEATURE_ID(aa64_sve2_pmull128, ARM_HWCAP2_A64_SVEPMULL);
+    GET_FEATURE_ID(aa64_sve2_bitperm, ARM_HWCAP2_A64_SVEBITPERM);
+    GET_FEATURE_ID(aa64_sve2_sha3, ARM_HWCAP2_A64_SVESHA3);
+    GET_FEATURE_ID(aa64_sve2_sm4, ARM_HWCAP2_A64_SVESM4);
+    GET_FEATURE_ID(aa64_condm_5, ARM_HWCAP2_A64_FLAGM2);
+    GET_FEATURE_ID(aa64_frint, ARM_HWCAP2_A64_FRINT);
+    GET_FEATURE_ID(aa64_sve_i8mm, ARM_HWCAP2_A64_SVEI8MM);
+    GET_FEATURE_ID(aa64_sve_f32mm, ARM_HWCAP2_A64_SVEF32MM);
+    GET_FEATURE_ID(aa64_sve_f64mm, ARM_HWCAP2_A64_SVEF64MM);
+    GET_FEATURE_ID(aa64_sve_bf16, ARM_HWCAP2_A64_SVEBF16);
+    GET_FEATURE_ID(aa64_i8mm, ARM_HWCAP2_A64_I8MM);
+    GET_FEATURE_ID(aa64_bf16, ARM_HWCAP2_A64_BF16);
+    GET_FEATURE_ID(aa64_rndr, ARM_HWCAP2_A64_RNG);
+    GET_FEATURE_ID(aa64_bti, ARM_HWCAP2_A64_BTI);
+    GET_FEATURE_ID(aa64_mte, ARM_HWCAP2_A64_MTE);
+
+    return hwcaps;
+}
+
+#undef GET_FEATURE_ID
+
 #endif /* TARGET_ARCH_ELF_H */
-- 
2.34.1

[PATCH 17/23] Add ARM AArch64 sigcode setup function for bsd-user

[Ajeet Singh]

From: Stacey Son <sson@FreeBSD.org>

signal trampoline function initializes a sequence of instructions
to handle signal returns and exits, and copies this code to the target offset.

Signed-off-by: Stacey Son <sson@FreeBSD.org>
Signed-off-by: Ajeet Singh <itachis@FreeBSD.org>
---
 bsd-user/aarch64/target_arch_sigtramp.h | 48 +++++++++++++++++++++++++
 1 file changed, 48 insertions(+)
 create mode 100644 bsd-user/aarch64/target_arch_sigtramp.h

diff --git a/bsd-user/aarch64/target_arch_sigtramp.h b/bsd-user/aarch64/target_arch_sigtramp.h
new file mode 100644
index 0000000000..8cdd33b621
--- /dev/null
+++ b/bsd-user/aarch64/target_arch_sigtramp.h
@@ -0,0 +1,48 @@
+/*
+ * ARM AArch64 sigcode for bsd-user
+ *
+ * Copyright (c) 2015 Stacey D. Son <sson at FreeBSD>
+ *
+ * This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Lesser General Public
+ * License as published by the Free Software Foundation; either
+ * version 2 of the License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with this library; if not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef TARGET_ARCH_SIGTRAMP_H
+#define TARGET_ARCH_SIGTRAMP_H
+
+/* Compare to ENTRY(sigcode) in arm64/arm64/locore.S */
+static inline abi_long setup_sigtramp(abi_ulong offset, unsigned sigf_uc,
+        unsigned sys_sigreturn)
+{
+    int i;
+    uint32_t sys_exit = TARGET_FREEBSD_NR_exit;
+
+    uint32_t sigtramp_code[] = {
+    /* 1 */ 0x910003e0,                 /* mov x0, sp */
+    /* 2 */ 0x91000000 + (sigf_uc << 10), /* add x0, x0, #SIGF_UC */
+    /* 3 */ 0xd2800000 + (sys_sigreturn << 5) + 0x8, /* mov x8, #SYS_sigreturn */
+    /* 4 */ 0xd4000001,                 /* svc #0 */
+    /* 5 */ 0xd2800028 + (sys_exit << 5) + 0x8, /* mov x8, #SYS_exit */
+    /* 6 */ 0xd4000001,                 /* svc #0 */
+    /* 7 */ 0x17fffffc,                 /* b -4 */
+    /* 8 */ sys_sigreturn,
+    /* 9 */ sys_exit
+    };
+
+    for (i = 0; i < 9; i++) {
+        tswap32s(&sigtramp_code[i]);
+    }
+
+    return memcpy_to_target(offset, sigtramp_code, TARGET_SZSIGCODE);
+}
+#endif /* TARGET_ARCH_SIGTRAMP_H */
-- 
2.34.1

[PATCH 18/23] Add ARM AArch64 specific signal definitions for bsd-user

[Ajeet Singh]

From: Stacey Son <sson@FreeBSD.org>

Defined register indices and sizes,introduced structures to represent
general purpose registers, floating point registers, and machine context

Signed-off-by: Stacey Son <sson@FreeBSD.org>
Signed-off-by: Warner Losh <imp@bsdimp.com>
Signed-off-by: Ajeet Singh <itachis@FreeBSD.org>
Co-authored-by: Warner Losh <imp@bsdimp.com>
---
 bsd-user/aarch64/target_arch_signal.h | 80 +++++++++++++++++++++++++++
 1 file changed, 80 insertions(+)
 create mode 100644 bsd-user/aarch64/target_arch_signal.h

diff --git a/bsd-user/aarch64/target_arch_signal.h b/bsd-user/aarch64/target_arch_signal.h
new file mode 100644
index 0000000000..df17173316
--- /dev/null
+++ b/bsd-user/aarch64/target_arch_signal.h
@@ -0,0 +1,80 @@
+/*
+ * ARM AArch64 specific signal definitions for bsd-user
+ *
+ * Copyright (c) 2015 Stacey D. Son <sson at FreeBSD>
+ *
+ * This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Lesser General Public
+ * License as published by the Free Software Foundation; either
+ * version 2 of the License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with this library; if not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef TARGET_ARCH_SIGNAL_H
+#define TARGET_ARCH_SIGNAL_H
+
+#include "cpu.h"
+
+#define TARGET_REG_X0   0
+#define TARGET_REG_X30  30
+#define TARGET_REG_X31  31
+#define TARGET_REG_LR   TARGET_REG_X30
+#define TARGET_REG_SP   TARGET_REG_X31
+
+#define TARGET_INSN_SIZE    4       /* arm64 instruction size */
+
+/* Size of the signal trampolin code. See _sigtramp(). */
+#define TARGET_SZSIGCODE    ((abi_ulong)(9 * TARGET_INSN_SIZE))
+
+/* compare to sys/arm64/include/_limits.h */
+#define TARGET_MINSIGSTKSZ  (1024 * 4)                  /* min sig stack size */
+#define TARGET_SIGSTKSZ     (TARGET_MINSIGSTKSZ + 32768)  /* recommended size */
+
+/* struct __mcontext in sys/arm64/include/ucontext.h */
+
+struct target_gpregs {
+    uint64_t    gp_x[30];
+    uint64_t    gp_lr;
+    uint64_t    gp_sp;
+    uint64_t    gp_elr;
+    uint32_t    gp_spsr;
+    uint32_t    gp_pad;
+};
+
+struct target_fpregs {
+    __uint128_t fp_q[32];
+    uint32_t    fp_sr;
+    uint32_t    fp_cr;
+    uint32_t    fp_flags;
+    uint32_t    fp_pad;
+};
+
+struct target__mcontext {
+    struct target_gpregs mc_gpregs;
+    struct target_fpregs mc_fpregs;
+    uint32_t    mc_flags;
+#define TARGET_MC_FP_VALID  0x1
+    uint32_t    mc_pad;
+    uint64_t    mc_spare[8];
+};
+
+typedef struct target__mcontext target_mcontext_t;
+
+#define TARGET_MCONTEXT_SIZE 880
+#define TARGET_UCONTEXT_SIZE 960
+
+#include "target_os_ucontext.h"
+
+struct target_sigframe {
+    target_siginfo_t    sf_si;  /* saved siginfo */
+    target_ucontext_t   sf_uc;  /* saved ucontext */
+};
+
+#endif /* TARGET_ARCH_SIGNAL_H */
-- 
2.34.1

[PATCH 19/23] Add ARM AArch64 signal trampoline argument setup for bsd-user

[Ajeet Singh]

From: Stacey Son <sson@FreeBSD.org>

function to set up signal handler arguments it populates
register values in `CPUARMState` based on the provided
signal, signal frame, signal action, and frame address

Signed-off-by: Stacey Son <sson@FreeBSD.org>
Signed-off-by: Ajeet Singh <itachis@FreeBSD.org>
---
 bsd-user/aarch64/signal.c | 53 +++++++++++++++++++++++++++++++++++++++
 1 file changed, 53 insertions(+)
 create mode 100644 bsd-user/aarch64/signal.c

diff --git a/bsd-user/aarch64/signal.c b/bsd-user/aarch64/signal.c
new file mode 100644
index 0000000000..98861f9ab3
--- /dev/null
+++ b/bsd-user/aarch64/signal.c
@@ -0,0 +1,53 @@
+/*
+ * ARM AArch64 specific signal definitions for bsd-user
+ *
+ * Copyright (c) 2015 Stacey D. Son <sson at FreeBSD>
+ *
+ * This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Lesser General Public
+ * License as published by the Free Software Foundation; either
+ * version 2 of the License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with this library; if not, see <http://www.gnu.org/licenses/>.
+ */
+#include "qemu/osdep.h"
+
+#include "qemu.h"
+
+/*
+ * Compare to sendsig() in sys/arm64/arm64/machdep.c
+ * Assumes that target stack frame memory is locked.
+ */
+abi_long set_sigtramp_args(CPUARMState *regs, int sig,
+                           struct target_sigframe *frame,
+                           abi_ulong frame_addr,
+                           struct target_sigaction *ka)
+{
+    /*
+     * Arguments to signal handler:
+     *  x0 = signal number
+     *  x1 = siginfo pointer
+     *  x2 = ucontext pointer
+     *  pc/elr = signal handler pointer
+     *  sp = sigframe struct pointer
+     *  lr = sigtramp at base of user stack
+     */
+
+    regs->xregs[0] = sig;
+    regs->xregs[1] = frame_addr +
+        offsetof(struct target_sigframe, sf_si);
+    regs->xregs[2] = frame_addr +
+        offsetof(struct target_sigframe, sf_uc);
+
+    regs->pc = ka->_sa_handler;
+    regs->xregs[TARGET_REG_SP] = frame_addr;
+    regs->xregs[TARGET_REG_LR] = TARGET_PS_STRINGS - TARGET_SZSIGCODE;
+
+    return 0;
+}
-- 
2.34.1

[PATCH 20/23] Add get_mcontext function for ARM AArch64 in bsd-user

[Ajeet Singh]

From: Stacey Son <sson@FreeBSD.org>

function to retrieve machine context,it populates the provided
target_mcontext_t structure with information from the CPUARMState
registers

Signed-off-by: Stacey Son <sson@FreeBSD.org>
Signed-off-by: Ajeet Singh <itachis@FreeBSD.org>
Co-authored-by: Kyle Evans <kevans@FreeBSD.org>
---
 bsd-user/aarch64/signal.c | 30 ++++++++++++++++++++++++++++++
 1 file changed, 30 insertions(+)

diff --git a/bsd-user/aarch64/signal.c b/bsd-user/aarch64/signal.c
index 98861f9ab3..ab3bf8558a 100644
--- a/bsd-user/aarch64/signal.c
+++ b/bsd-user/aarch64/signal.c
@@ -51,3 +51,33 @@ abi_long set_sigtramp_args(CPUARMState *regs, int sig,
 
     return 0;
 }
+
+/*
+ * Compare to get_mcontext() in arm64/arm64/machdep.c
+ * Assumes that the memory is locked if mcp points to user memory.
+ */
+abi_long get_mcontext(CPUARMState *regs, target_mcontext_t *mcp, int flags)
+{
+    int err = 0, i;
+    uint64_t *gr = mcp->mc_gpregs.gp_x;
+
+    mcp->mc_gpregs.gp_spsr = pstate_read(regs);
+    if (flags & TARGET_MC_GET_CLEAR_RET) {
+        gr[0] = 0UL;
+        mcp->mc_gpregs.gp_spsr &= ~CPSR_C;
+    } else {
+        gr[0] = tswap64(regs->xregs[0]);
+    }
+
+    for (i = 1; i < 30; i++) {
+        gr[i] = tswap64(regs->xregs[i]);
+    }
+
+    mcp->mc_gpregs.gp_sp = tswap64(regs->xregs[TARGET_REG_SP]);
+    mcp->mc_gpregs.gp_lr = tswap64(regs->xregs[TARGET_REG_LR]);
+    mcp->mc_gpregs.gp_elr = tswap64(regs->pc);
+
+    /* XXX FP? */
+
+    return err;
+}
-- 
2.34.1

[PATCH 21/23] Add setup_sigframe_arch function for ARM AArch64 in bsd-user

[Ajeet Singh]

From: Warner Losh <imp@bsdimp.com>

The function utilizes the `get_mcontext` function to retrieve the machine
context for the current CPUARMState

Signed-off-by: Warner Losh <imp@bsdimp.com>
Signed-off-by: Ajeet Singh <itachis@FreeBSD.org>
---
 bsd-user/aarch64/signal.c | 14 ++++++++++++++
 1 file changed, 14 insertions(+)

diff --git a/bsd-user/aarch64/signal.c b/bsd-user/aarch64/signal.c
index ab3bf8558a..43c886e603 100644
--- a/bsd-user/aarch64/signal.c
+++ b/bsd-user/aarch64/signal.c
@@ -81,3 +81,17 @@ abi_long get_mcontext(CPUARMState *regs, target_mcontext_t *mcp, int flags)
 
     return err;
 }
+
+/*
+ * Compare to arm64/arm64/exec_machdep.c sendsig()
+ * Assumes that the memory is locked if frame points to user memory.
+ */
+abi_long setup_sigframe_arch(CPUARMState *env, abi_ulong frame_addr,
+                             struct target_sigframe *frame, int flags)
+{
+    target_mcontext_t *mcp = &frame->sf_uc.uc_mcontext;
+
+    get_mcontext(env, mcp, flags);
+    return 0;
+}
+
-- 
2.34.1

[PATCH 22/23] Add set_mcontext function for ARM AArch64 in bsd-user

[Ajeet Singh]

From: Stacey Son <sson@FreeBSD.org>

The function copies register values from the provided target_mcontext_t
structure to the CPUARMState registers

Signed-off-by: Stacey Son <sson@FreeBSD.org>
Signed-off-by: Ajeet Singh <itachis@FreeBSD.org>
---
 bsd-user/aarch64/signal.c | 22 ++++++++++++++++++++++
 1 file changed, 22 insertions(+)

diff --git a/bsd-user/aarch64/signal.c b/bsd-user/aarch64/signal.c
index 43c886e603..13faac8ce6 100644
--- a/bsd-user/aarch64/signal.c
+++ b/bsd-user/aarch64/signal.c
@@ -95,3 +95,25 @@ abi_long setup_sigframe_arch(CPUARMState *env, abi_ulong frame_addr,
     return 0;
 }
 
+/*
+ * Compare to set_mcontext() in arm64/arm64/machdep.c
+ * Assumes that the memory is locked if frame points to user memory.
+ */
+abi_long set_mcontext(CPUARMState *regs, target_mcontext_t *mcp, int srflag)
+{
+    int err = 0, i;
+    const uint64_t *gr = mcp->mc_gpregs.gp_x;
+
+    for (i = 0; i < 30; i++) {
+        regs->xregs[i] = tswap64(gr[i]);
+    }
+
+    regs->xregs[TARGET_REG_SP] = tswap64(mcp->mc_gpregs.gp_sp);
+    regs->xregs[TARGET_REG_LR] = tswap64(mcp->mc_gpregs.gp_lr);
+    regs->pc = mcp->mc_gpregs.gp_elr;
+    pstate_write(regs, mcp->mc_gpregs.gp_spsr);
+
+    /* XXX FP? */
+
+    return err;
+}
-- 
2.34.1

[PATCH 23/23] Add get_ucontext_sigreturn function

[Ajeet Singh]

From: Stacey Son <sson@FreeBSD.org>

Function checks the processor state to ensure that the current
execution mode is EL0 and no flags indicating interrupts or
exceptions are set

Signed-off-by: Stacey Son <sson@FreeBSD.org>
Signed-off-by: Ajeet Singh <itachis@FreeBSD.org>
---
 bsd-user/aarch64/signal.c | 18 ++++++++++++++++++
 1 file changed, 18 insertions(+)

diff --git a/bsd-user/aarch64/signal.c b/bsd-user/aarch64/signal.c
index 13faac8ce6..ad81531ec5 100644
--- a/bsd-user/aarch64/signal.c
+++ b/bsd-user/aarch64/signal.c
@@ -117,3 +117,21 @@ abi_long set_mcontext(CPUARMState *regs, target_mcontext_t *mcp, int srflag)
 
     return err;
 }
+
+/* Compare to sys_sigreturn() in  arm64/arm64/machdep.c */
+abi_long get_ucontext_sigreturn(CPUARMState *regs, abi_ulong target_sf,
+                                abi_ulong *target_uc)
+{
+    uint32_t pstate = pstate_read(regs);
+
+    *target_uc = 0;
+
+    if ((pstate & PSTATE_M) != PSTATE_MODE_EL0t  ||
+        (pstate & (PSTATE_F | PSTATE_I | PSTATE_A | PSTATE_D)) != 0) {
+        return -TARGET_EINVAL;
+    }
+
+    *target_uc = target_sf;
+
+    return 0;
+}
-- 
2.34.1

Re: [PATCH 01/23] Add CPU initialization function

[Richard Henderson]

On 6/17/24 11:57, Ajeet Singh wrote:
> From: Stacey Son <sson@FreeBSD.org>
> 
> Addded function to initialize ARM CPU
> and to check if it supports 64 bit mode
> 
> Signed-off-by: Ajeet Singh <itachis@FreeBSD.org>
> Signed-off-by: Stacey Son <sson@FreeBSD.org>
> ---
>   bsd-user/aarch64/target_arch_cpu.h | 42 ++++++++++++++++++++++++++++++
>   1 file changed, 42 insertions(+)
>   create mode 100644 bsd-user/aarch64/target_arch_cpu.h
> 
> diff --git a/bsd-user/aarch64/target_arch_cpu.h b/bsd-user/aarch64/target_arch_cpu.h
> new file mode 100644
> index 0000000000..db5c7062b9
> --- /dev/null
> +++ b/bsd-user/aarch64/target_arch_cpu.h
> @@ -0,0 +1,42 @@
> +/*
> + *  ARM AArch64 cpu init and loop
> + *
> + * Copyright (c) 2015 Stacey Son
> + *
> + * This library is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU Lesser General Public
> + * License as published by the Free Software Foundation; either
> + * version 2 of the License, or (at your option) any later version.
> + *
> + * This library is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
> + * Lesser General Public License for more details.
> + *
> + * You should have received a copy of the GNU Lesser General Public
> + * License along with this library; if not, see <http://www.gnu.org/licenses/>.
> + */
> +
> +#ifndef TARGET_ARCH_CPU_H
> +#define TARGET_ARCH_CPU_H
> +
> +#include "target_arch.h"
> +#include "target/arm/syndrome.h"

Do you actually need syndrome.h?

Otherwise,
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>

r~

> +
> +#define TARGET_DEFAULT_CPU_MODEL "any"
> +
> +static inline void target_cpu_init(CPUARMState *env,
> +    struct target_pt_regs *regs)
> +{
> +    int i;
> +
> +    if (!(arm_feature(env, ARM_FEATURE_AARCH64))) {
> +        fprintf(stderr, "The selected ARM CPU does not support 64 bit mode\n");
> +        exit(1);
> +    }
> +    for (i = 0; i < 31; i++) {
> +        env->xregs[i] = regs->regs[i];
> +    }
> +    env->pc = regs->pc;
> +    env->xregs[31] = regs->sp;
> +}

Re: [PATCH 02/23] Added CPU loop function

[Richard Henderson]

On 6/17/24 11:57, Ajeet Singh wrote:
> +            /*
> +             * The carry bit is cleared for no error; set for error.
> +             * See arm64/arm64/vm_machdep.c cpu_set_syscall_retval()
> +             */
> +            pstate = pstate_read(env);
> +            if (ret >= 0) {
> +                pstate &= ~PSTATE_C;
> +                env->xregs[0] = ret;
> +            } else if (ret == -TARGET_ERESTART) {
> +                env->pc -= 4;
> +                break;
> +            } else if (ret != -TARGET_EJUSTRETURN) {
> +                pstate |= PSTATE_C;
> +                env->xregs[0] = -ret;
> +            }
> +            pstate_write(env, pstate);

No need for full pstate read/write:

     env->CF = {0,1};


> +            break;
> +
> +        case EXCP_INTERRUPT:
> +            /* Just indicate that signals should be handle ASAP. */
> +            break;
> +
> +        case EXCP_UDEF:
> +            force_sig_fault(TARGET_SIGILL, TARGET_ILL_ILLOPN, env->pc);
> +            break;
> +
> +
> +        case EXCP_PREFETCH_ABORT:
> +        case EXCP_DATA_ABORT:
> +            /* We should only arrive here with EC in {DATAABORT, INSNABORT}. */
> +            ec = syn_get_ec(env->exception.syndrome);

Nevermind about my question about syndrome.h vs patch 1.


r~

Re: [PATCH 03/23] Added function to clone CPU state

[Richard Henderson]

On 6/17/24 11:57, Ajeet Singh wrote:
> From: Stacey Son<sson@FreeBSD.org>
> 
> Function can copy cpu state to create new thread
> 
> Signed-off-by: Stacey Son<sson@FreeBSD.org>
> Signed-off-by: Ajeet Singh<itachis@FreeBSD.org>
> ---
>   bsd-user/aarch64/target_arch_cpu.h | 17 +++++++++++++++++
>   1 file changed, 17 insertions(+)

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>

r~

Re: [PATCH 04/23] AArch64 specific CPU for bsd-user

[Richard Henderson]

On 6/17/24 11:57, Ajeet Singh wrote:
> From: Stacey Son <sson@FreeBSD.org>
> 
> Function to set and recieve thread-local-storage value
> from tpidr_el0 register
> 
> Signed-off-by: Stacey Son <sson@FreeBSD.org>
> Signed-off-by: Ajeet Singh <itachis@FreeBSD.org>
> ---
>   bsd-user/aarch64/target_arch_cpu.c | 34 ++++++++++++++++++++++++++++++
>   1 file changed, 34 insertions(+)
>   create mode 100644 bsd-user/aarch64/target_arch_cpu.c
> 
> diff --git a/bsd-user/aarch64/target_arch_cpu.c b/bsd-user/aarch64/target_arch_cpu.c
> new file mode 100644
> index 0000000000..70ef651827
> --- /dev/null
> +++ b/bsd-user/aarch64/target_arch_cpu.c
> @@ -0,0 +1,34 @@
> +/*
> + * ARM AArch64 specific CPU for bsd-user
> + *
> + * Copyright (c) 2015 Stacey Son
> + *
> + * This library is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU Lesser General Public
> + * License as published by the Free Software Foundation; either
> + * version 2 of the License, or (at your option) any later version.
> + *
> + * This library is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
> + * Lesser General Public License for more details.
> + *
> + * You should have received a copy of the GNU Lesser General Public
> + * License along with this library; if not, see <http://www.gnu.org/licenses/>.
> + */
> +#include "qemu/osdep.h"
> +
> +#include "target_arch.h"
> +
> +/* See cpu_set_user_tls() in arm64/arm64/vm_machdep.c */
> +void target_cpu_set_tls(CPUARMState *env, target_ulong newtls)
> +{
> +
> +    env->cp15.tpidr_el[0] = newtls;

Extra newline.

Otherwise,
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>

r~

Re: [PATCH 05/23] Managing CPU register for BSD-USER

[Richard Henderson]

On 6/17/24 11:57, Ajeet Singh wrote:
> From: Stacey Son<sson@FreeBSD.org>
> 
> Added structure for storing register states
> 
> Signed-off-by: Stacey Son<sson@FreeBSD.org>
> Signed-off-by: Ajeet Singh<itachis@FreeBSD.org>
> Co-authored-by: Sean Bruno<sbruno@freebsd.org>
> ---
>   bsd-user/aarch64/target_syscall.h | 51 +++++++++++++++++++++++++++++++
>   1 file changed, 51 insertions(+)
>   create mode 100644 bsd-user/aarch64/target_syscall.h

Acked-by: Richard Henderson <richard.henderson@linaro.org>

r~

Re: [PATCH 06/23] Add Aarch64 register handling

[Richard Henderson]

On 6/17/24 11:57, Ajeet Singh wrote:
> From: Stacey Son <sson@FreeBSD.org>
> 
> Header file for managing CPU register states in
> FreeBSD user mode
> 
> Signed-off-by: Stacey Son <sson@FreeBSD.org>
> Signed-off-by: Ajeet Singh <itachis@FreeBSD.org>
> ---
>   bsd-user/aarch64/target_arch_reg.h | 56 ++++++++++++++++++++++++++++++
>   1 file changed, 56 insertions(+)
>   create mode 100644 bsd-user/aarch64/target_arch_reg.h
> 
> diff --git a/bsd-user/aarch64/target_arch_reg.h b/bsd-user/aarch64/target_arch_reg.h
> new file mode 100644
> index 0000000000..5c7154f0c1
> --- /dev/null
> +++ b/bsd-user/aarch64/target_arch_reg.h
> @@ -0,0 +1,56 @@
> +/*
> + *  FreeBSD arm64 register structures
> + *
> + *  Copyright (c) 2015 Stacey Son
> + *  All rights reserved.
> + *
> + *  This program is free software; you can redistribute it and/or modify
> + *  it under the terms of the GNU General Public License as published by
> + *  the Free Software Foundation; either version 2 of the License, or
> + *  (at your option) any later version.
> + *
> + *  This program is distributed in the hope that it will be useful,
> + *  but WITHOUT ANY WARRANTY; without even the implied warranty of
> + *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> + *  GNU General Public License for more details.
> + *
> + *  You should have received a copy of the GNU General Public License
> + *  along with this program; if not, see <http://www.gnu.org/licenses/>.
> + */
> +
> +#ifndef TARGET_ARCH_REG_H
> +#define TARGET_ARCH_REG_H
> +
> +/* See sys/arm64/include/reg.h */
> +typedef struct target_reg {
> +    uint64_t        x[30];
> +    uint64_t        lr;
> +    uint64_t        sp;
> +    uint64_t        elr;
> +    uint64_t        spsr;
> +} target_reg_t;
> +
> +typedef struct target_fpreg {
> +    __uint128_t     fp_q[32];

I'm not keen on this, though possibly it doesn't matter for hosts that bsd-user is 
intended to support.  Better as either Int128 or uint64_t fp_q[32][2].

What is this structure used for within qemu?
Does freebsd support SVE yet?

It's certainly not used with this patch, so it's hard to tell, but can we omit it entirely 
for now?


r~

Re: [PATCH 07/23] Add ARM AArch64 TLS Management Prototypes for BSD-User

[Richard Henderson]

On 6/17/24 11:57, Ajeet Singh wrote:
> From: Stacey Son <sson@FreeBSD.org>
> 
> Prototypes for setting and getting TLS( thread local storage)
> 
> Signed-off-by: Stacey Son <sson@FreeBSD.org>
> Signed-off-by: Ajeet Singh <itachis@FreeBSD.org>
> ---
>   bsd-user/aarch64/target_arch.h | 28 ++++++++++++++++++++++++++++
>   1 file changed, 28 insertions(+)
>   create mode 100644 bsd-user/aarch64/target_arch.h
> 
> diff --git a/bsd-user/aarch64/target_arch.h b/bsd-user/aarch64/target_arch.h
> new file mode 100644
> index 0000000000..27f47de8eb
> --- /dev/null
> +++ b/bsd-user/aarch64/target_arch.h
> @@ -0,0 +1,28 @@
> +/*
> + * ARM AArch64 specific prototypes for bsd-user
> + *
> + * Copyright (c) 2015 Stacey D. Son <sson at FreeBSD>
> + *
> + * This library is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU Lesser General Public
> + * License as published by the Free Software Foundation; either
> + * version 2 of the License, or (at your option) any later version.
> + *
> + * This library is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
> + * Lesser General Public License for more details.
> + *
> + * You should have received a copy of the GNU Lesser General Public
> + * License along with this library; if not, see <http://www.gnu.org/licenses/>.
> + */
> +
> +#ifndef TARGET_ARCH_H
> +#define TARGET_ARCH_H
> +
> +#include "qemu.h"
> +
> +void target_cpu_set_tls(CPUARMState *env, target_ulong newtls);
> +target_ulong target_cpu_get_tls(CPUARMState *env);
> +
> +#endif /* TARGET_ARCH_H */

Acked-by: Richard Henderson <richard.henderson@linaro.org>

I suggest that these declarations use CPUArchState, and be made common for all targets.

r~

Re: [PATCH 08/23] Add Aarch64 sysarch() system call emulation for BSD-USER

[Richard Henderson]

On 6/17/24 11:57, Ajeet Singh wrote:
> From: Stacey Son<sson@FreeBSD.org>
> 
> Initial implementation of sysarch() syscall and a printing function
> 
> Signed-off-by: Stacey Son<sson@FreeBSD.org>
> Signed-off-by: Ajeet Singh<itachis@FreeBSD.org>
> ---
>   bsd-user/aarch64/target_arch_sysarch.h | 42 ++++++++++++++++++++++++++
>   1 file changed, 42 insertions(+)
>   create mode 100644 bsd-user/aarch64/target_arch_sysarch.h

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>

r~

Re: [PATCH 09/23] Add thread setup for BSD-USER

[Richard Henderson]

On 6/17/24 11:57, Ajeet Singh wrote:
> From: Stacey Son <sson@FreeBSD.org>
> 
> Function for setting up thread upcall which will
> add thread support to BSD-User
> 
> Signed-off-by: Stacey Son <sson@FreeBSD.org>
> Signed-off-by: Ajeet Singh <itachis@FreeBSD.org>
> Co-authored-by: Jessica Clarke <jrtc27@jrtc27.com>
> ---
>   bsd-user/aarch64/target_arch_thread.h | 45 +++++++++++++++++++++++++++
>   1 file changed, 45 insertions(+)
>   create mode 100644 bsd-user/aarch64/target_arch_thread.h
> 
> diff --git a/bsd-user/aarch64/target_arch_thread.h b/bsd-user/aarch64/target_arch_thread.h
> new file mode 100644
> index 0000000000..d2f2dea7ce
> --- /dev/null
> +++ b/bsd-user/aarch64/target_arch_thread.h
> @@ -0,0 +1,45 @@
> +/*
> + * ARM AArch64 thread support for bsd-user.
> + *
> + * Copyright (c) 2015 Stacey D. Son <sson at FreeBSD>
> + *
> + * This library is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU Lesser General Public
> + * License as published by the Free Software Foundation; either
> + * version 2 of the License, or (at your option) any later version.
> + *
> + * This library is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
> + * Lesser General Public License for more details.
> + *
> + * You should have received a copy of the GNU Lesser General Public
> + * License along with this library; if not, see <http://www.gnu.org/licenses/>.
> + */
> +
> +#ifndef TARGET_ARCH_THREAD_H
> +#define TARGET_ARCH_THREAD_H
> +
> +/* Compare to arm64/arm64/vm_machdep.c cpu_set_upcall_kse() */
> +static inline void target_thread_set_upcall(CPUARMState *regs, abi_ulong entry,
> +    abi_ulong arg, abi_ulong stack_base, abi_ulong stack_size)
> +{
> +    abi_ulong sp;
> +
> +    /*
> +     * Make sure the stack is properly aligned.
> +     * arm64/include/param.h (STACKLIGN() macro)
> +     */
> +    sp = (abi_ulong)(stack_base + stack_size) & ~(16 - 1);

sp = ROUND_DOWN(stack_base + stack_size, 16);

> +    pstate_write(regs, PSTATE_MODE_EL0t);

This is the default in arm_cpu_reset_hold for user-only.
There should be no need to duplicate this.


r~

Re: [PATCH 10/23] Add thread initialization for BSD-USER

[Richard Henderson]

On 6/17/24 11:57, Ajeet Singh wrote:
> From: Stacey Son <sson@FreeBSD.org>
> 
> Initializes thread's register state
> 
> Signed-off-by: Stacey Son <sson@FreeBSD.org>
> Signed-off-by: Ajeet Singh <itachis@FreeBSD.org>
> Co-authored-by: Jessica Clarke <jrtc27@jrtc27.com>
> ---
>   bsd-user/aarch64/target_arch_thread.h | 16 ++++++++++++++++
>   1 file changed, 16 insertions(+)
> 
> diff --git a/bsd-user/aarch64/target_arch_thread.h b/bsd-user/aarch64/target_arch_thread.h
> index d2f2dea7ce..bfc9050cb1 100644
> --- a/bsd-user/aarch64/target_arch_thread.h
> +++ b/bsd-user/aarch64/target_arch_thread.h
> @@ -42,4 +42,20 @@ static inline void target_thread_set_upcall(CPUARMState *regs, abi_ulong entry,
>       pstate_write(regs, PSTATE_MODE_EL0t);
>   }
>   
> +static inline void target_thread_init(struct target_pt_regs *regs,
> +        struct image_info *infop)
> +{
> +    abi_long stack = infop->start_stack;
> +
> +    /*
> +     * Make sure the stack is properly aligned.
> +     * arm64/include/param.h (STACKLIGN() macro)
> +     */
> +
> +    memset(regs, 0, sizeof(*regs));
> +    regs->regs[0] = infop->start_stack;
> +    regs->pc = infop->entry;
> +    regs->sp = stack & ~(16 - 1);

ROUND_DOWN, otherwise,
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>


r~

Re: [PATCH 11/23] Update ARM AArch64 VM parameter definitions for bsd-user

[Richard Henderson]

On 6/17/24 11:57, Ajeet Singh wrote:
> From: Stacey Son <sson@FreeBSD.org>
> 
> Defined address spaces for FreeBSD/arm64 and added function for
> getting stack pointer from CPU and setting a return value.
> 
> Signed-off-by: Stacey Son <sson@FreeBSD.org>
> Signed-off-by: Warner Losh <imp@bsdimp.com>
> Signed-off-by: Ajeet Singh <itachis@FreeBSD.org>
> Co-authored-by: Sean Bruno <sbruno@freebsd.org>
> Co-authored-by: Warner Losh <imp@bsdimp.com>
> ---
>   bsd-user/aarch64/target_arch_vmparam.h | 68 ++++++++++++++++++++++++++
>   1 file changed, 68 insertions(+)
>   create mode 100644 bsd-user/aarch64/target_arch_vmparam.h

Acked-by: Richard Henderson <richard.henderson@linaro.org>

> +                /* KERNBASE - 512 MB */
> +#define TARGET_VM_MAXUSER_ADDRESS   (0x00007fffff000000ULL - (512 * MiB))
> +#define TARGET_USRSTACK             TARGET_VM_MAXUSER_ADDRESS

I will note that this may conflict with -R reserved_size,
and is an existing issue with the x86_64 port as well.


r~

Re: [PATCH 12/23] Add ability to get rval2

[Richard Henderson]

On 6/17/24 11:57, Ajeet Singh wrote:
> From: Warner Losh <imp@bsdimp.com>
> 
> Function accesses the x1 register which holds the value
> 
> Signed-off-by: Warner Losh <imp@bsdimp.com>
> Signed-off-by: Ajeet Singh <itachis@FreeBSD.org>
> ---
>   bsd-user/aarch64/target_arch_vmparam.h | 6 ++++++
>   1 file changed, 6 insertions(+)
> 
> diff --git a/bsd-user/aarch64/target_arch_vmparam.h b/bsd-user/aarch64/target_arch_vmparam.h
> index dc66e1289b..0c35491970 100644
> --- a/bsd-user/aarch64/target_arch_vmparam.h
> +++ b/bsd-user/aarch64/target_arch_vmparam.h
> @@ -65,4 +65,10 @@ static inline void set_second_rval(CPUARMState *state, abi_ulong retval2)
>   {
>       state->xregs[1] = retval2; /* XXX not really used on 64-bit arch */
>   }
> +
> +static inline abi_ulong get_second_rval(CPUARMState *state)
> +{
> +    return state->xregs[1];
> +}

The other two ports only define set_second_rval, and this one only defines get?  This 
doesn't seem right...


r~

Re: [PATCH 13/23] Add ARM AArch64 ELF definitions for bsd-user

[Richard Henderson]

On 6/17/24 11:57, Ajeet Singh wrote:
> From: Stacey Son<sson@FreeBSD.org>
> 
> Defined mmap and dynamic load adresses and
> set various elf parameters
> 
> Signed-off-by: Stacey Son<sson@FreeBSD.org>
> Signed-off-by: Ajeet Singh<itachis@FreeBSD.org>
> Co-authored-by: Kyle Evans<kevans@FreeBSD.org>
> ---
>   bsd-user/aarch64/target_arch_elf.h | 37 ++++++++++++++++++++++++++++++
>   1 file changed, 37 insertions(+)
>   create mode 100644 bsd-user/aarch64/target_arch_elf.h

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>

r~

Re: [PATCH 14/23] Add ARM AArch64 hardware capability definitions

[Richard Henderson]

On 6/17/24 11:57, Ajeet Singh wrote:
> From: Warner Losh<imp@bsdimp.com>
> 
> Defined a huge list of hardware capabilites and added
> macros for retrieving hwcap flags
> 
> Signed-off-by: Warner Losh<imp@bsdimp.com>
> Signed-off-by: Ajeet Singh<itachis@FreeBSD.org>
> ---
>   bsd-user/aarch64/target_arch_elf.h | 61 ++++++++++++++++++++++++++++++
>   1 file changed, 61 insertions(+)

Acked-by: Richard Henderson <richard.henderson@linaro.org>

r~

Re: [PATCH 15/23] Add function to retrieve ARM AArch64 hardware capabilities

[Richard Henderson]

On 6/17/24 11:57, Ajeet Singh wrote:
> From: Warner Losh<imp@bsdimp.com>
> 
> The function initializes default hardware capabilities and
> finds additional features using the `GET_FEATURE_ID` macro
> 
> Signed-off-by: Warner Losh<imp@bsdimp.com>
> Signed-off-by: Ajeet Singh<itachis@FreeBSD.org>
> ---
>   bsd-user/aarch64/target_arch_elf.h | 38 ++++++++++++++++++++++++++++++
>   1 file changed, 38 insertions(+)

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>

r~

Re: [PATCH 16/23] Add function to retrieve additional ARM AArch64 hwcap

[Richard Henderson]

On 6/17/24 11:57, Ajeet Singh wrote:
> From: Warner Losh<imp@bsdimp.com>
> 
> Function to retrieve the extended hardware capability flags
> 
> Signed-off-by: Warner Losh<imp@bsdimp.com>
> Signed-off-by: Ajeet Singh<itachis@FreeBSD.org>
> ---
>   bsd-user/aarch64/target_arch_elf.h | 29 +++++++++++++++++++++++++++++
>   1 file changed, 29 insertions(+)

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>

r~

Re: [PATCH 17/23] Add ARM AArch64 sigcode setup function for bsd-user

[Richard Henderson]

On 6/17/24 11:57, Ajeet Singh wrote:
> From: Stacey Son <sson@FreeBSD.org>
> 
> signal trampoline function initializes a sequence of instructions
> to handle signal returns and exits, and copies this code to the target offset.
> 
> Signed-off-by: Stacey Son <sson@FreeBSD.org>
> Signed-off-by: Ajeet Singh <itachis@FreeBSD.org>
> ---
>   bsd-user/aarch64/target_arch_sigtramp.h | 48 +++++++++++++++++++++++++
>   1 file changed, 48 insertions(+)
>   create mode 100644 bsd-user/aarch64/target_arch_sigtramp.h
> 
> diff --git a/bsd-user/aarch64/target_arch_sigtramp.h b/bsd-user/aarch64/target_arch_sigtramp.h
> new file mode 100644
> index 0000000000..8cdd33b621
> --- /dev/null
> +++ b/bsd-user/aarch64/target_arch_sigtramp.h
> @@ -0,0 +1,48 @@
> +/*
> + * ARM AArch64 sigcode for bsd-user
> + *
> + * Copyright (c) 2015 Stacey D. Son <sson at FreeBSD>
> + *
> + * This library is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU Lesser General Public
> + * License as published by the Free Software Foundation; either
> + * version 2 of the License, or (at your option) any later version.
> + *
> + * This library is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
> + * Lesser General Public License for more details.
> + *
> + * You should have received a copy of the GNU Lesser General Public
> + * License along with this library; if not, see <http://www.gnu.org/licenses/>.
> + */
> +
> +#ifndef TARGET_ARCH_SIGTRAMP_H
> +#define TARGET_ARCH_SIGTRAMP_H
> +
> +/* Compare to ENTRY(sigcode) in arm64/arm64/locore.S */
> +static inline abi_long setup_sigtramp(abi_ulong offset, unsigned sigf_uc,
> +        unsigned sys_sigreturn)
> +{
> +    int i;
> +    uint32_t sys_exit = TARGET_FREEBSD_NR_exit;
> +
> +    uint32_t sigtramp_code[] = {
> +    /* 1 */ 0x910003e0,                 /* mov x0, sp */
> +    /* 2 */ 0x91000000 + (sigf_uc << 10), /* add x0, x0, #SIGF_UC */
> +    /* 3 */ 0xd2800000 + (sys_sigreturn << 5) + 0x8, /* mov x8, #SYS_sigreturn */
> +    /* 4 */ 0xd4000001,                 /* svc #0 */
> +    /* 5 */ 0xd2800028 + (sys_exit << 5) + 0x8, /* mov x8, #SYS_exit */
> +    /* 6 */ 0xd4000001,                 /* svc #0 */
> +    /* 7 */ 0x17fffffc,                 /* b -4 */
> +    /* 8 */ sys_sigreturn,
> +    /* 9 */ sys_exit
> +    };
> +
> +    for (i = 0; i < 9; i++) {
> +        tswap32s(&sigtramp_code[i]);
> +    }

You can use const_le32() to initialize sigtramp_code[], at which point it can be static const.

I'll note that bsd-user/arm/ could be improved the same way.  In addition, the g_assert in 
arm/ can be QEMU_BUILD_BUG_ON instead, to be caught at compile-time.


r~

Re: [PATCH 18/23] Add ARM AArch64 specific signal definitions for bsd-user

[Richard Henderson]

On 6/17/24 11:57, Ajeet Singh wrote:
> From: Stacey Son <sson@FreeBSD.org>
> 
> Defined register indices and sizes,introduced structures to represent
> general purpose registers, floating point registers, and machine context
> 
> Signed-off-by: Stacey Son <sson@FreeBSD.org>
> Signed-off-by: Warner Losh <imp@bsdimp.com>
> Signed-off-by: Ajeet Singh <itachis@FreeBSD.org>
> Co-authored-by: Warner Losh <imp@bsdimp.com>
> ---
>   bsd-user/aarch64/target_arch_signal.h | 80 +++++++++++++++++++++++++++
>   1 file changed, 80 insertions(+)
>   create mode 100644 bsd-user/aarch64/target_arch_signal.h
> 
> diff --git a/bsd-user/aarch64/target_arch_signal.h b/bsd-user/aarch64/target_arch_signal.h
> new file mode 100644
> index 0000000000..df17173316
> --- /dev/null
> +++ b/bsd-user/aarch64/target_arch_signal.h
> @@ -0,0 +1,80 @@
> +/*
> + * ARM AArch64 specific signal definitions for bsd-user
> + *
> + * Copyright (c) 2015 Stacey D. Son <sson at FreeBSD>
> + *
> + * This library is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU Lesser General Public
> + * License as published by the Free Software Foundation; either
> + * version 2 of the License, or (at your option) any later version.
> + *
> + * This library is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
> + * Lesser General Public License for more details.
> + *
> + * You should have received a copy of the GNU Lesser General Public
> + * License along with this library; if not, see <http://www.gnu.org/licenses/>.
> + */
> +
> +#ifndef TARGET_ARCH_SIGNAL_H
> +#define TARGET_ARCH_SIGNAL_H
> +
> +#include "cpu.h"
> +
> +#define TARGET_REG_X0   0
> +#define TARGET_REG_X30  30
> +#define TARGET_REG_X31  31
> +#define TARGET_REG_LR   TARGET_REG_X30
> +#define TARGET_REG_SP   TARGET_REG_X31
> +
> +#define TARGET_INSN_SIZE    4       /* arm64 instruction size */
> +
> +/* Size of the signal trampolin code. See _sigtramp(). */
> +#define TARGET_SZSIGCODE    ((abi_ulong)(9 * TARGET_INSN_SIZE))
> +
> +/* compare to sys/arm64/include/_limits.h */
> +#define TARGET_MINSIGSTKSZ  (1024 * 4)                  /* min sig stack size */
> +#define TARGET_SIGSTKSZ     (TARGET_MINSIGSTKSZ + 32768)  /* recommended size */
> +
> +/* struct __mcontext in sys/arm64/include/ucontext.h */
> +
> +struct target_gpregs {
> +    uint64_t    gp_x[30];
> +    uint64_t    gp_lr;
> +    uint64_t    gp_sp;
> +    uint64_t    gp_elr;
> +    uint32_t    gp_spsr;
> +    uint32_t    gp_pad;
> +};
> +
> +struct target_fpregs {
> +    __uint128_t fp_q[32];

Per patch 6, re not using __uint128_t directly.


r~

Re: [PATCH 19/23] Add ARM AArch64 signal trampoline argument setup for bsd-user

[Richard Henderson]

On 6/17/24 11:58, Ajeet Singh wrote:
> From: Stacey Son<sson@FreeBSD.org>
> 
> function to set up signal handler arguments it populates
> register values in `CPUARMState` based on the provided
> signal, signal frame, signal action, and frame address
> 
> Signed-off-by: Stacey Son<sson@FreeBSD.org>
> Signed-off-by: Ajeet Singh<itachis@FreeBSD.org>
> ---
>   bsd-user/aarch64/signal.c | 53 +++++++++++++++++++++++++++++++++++++++
>   1 file changed, 53 insertions(+)
>   create mode 100644 bsd-user/aarch64/signal.c

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>

r~

Re: [PATCH 20/23] Add get_mcontext function for ARM AArch64 in bsd-user

[Richard Henderson]

On 6/17/24 11:58, Ajeet Singh wrote:
> From: Stacey Son <sson@FreeBSD.org>
> 
> function to retrieve machine context,it populates the provided
> target_mcontext_t structure with information from the CPUARMState
> registers
> 
> Signed-off-by: Stacey Son <sson@FreeBSD.org>
> Signed-off-by: Ajeet Singh <itachis@FreeBSD.org>
> Co-authored-by: Kyle Evans <kevans@FreeBSD.org>
> ---
>   bsd-user/aarch64/signal.c | 30 ++++++++++++++++++++++++++++++
>   1 file changed, 30 insertions(+)
> 
> diff --git a/bsd-user/aarch64/signal.c b/bsd-user/aarch64/signal.c
> index 98861f9ab3..ab3bf8558a 100644
> --- a/bsd-user/aarch64/signal.c
> +++ b/bsd-user/aarch64/signal.c
> @@ -51,3 +51,33 @@ abi_long set_sigtramp_args(CPUARMState *regs, int sig,
>   
>       return 0;
>   }
> +
> +/*
> + * Compare to get_mcontext() in arm64/arm64/machdep.c
> + * Assumes that the memory is locked if mcp points to user memory.
> + */
> +abi_long get_mcontext(CPUARMState *regs, target_mcontext_t *mcp, int flags)
> +{
> +    int err = 0, i;
> +    uint64_t *gr = mcp->mc_gpregs.gp_x;
> +
> +    mcp->mc_gpregs.gp_spsr = pstate_read(regs);
> +    if (flags & TARGET_MC_GET_CLEAR_RET) {
> +        gr[0] = 0UL;
> +        mcp->mc_gpregs.gp_spsr &= ~CPSR_C;
> +    } else {
> +        gr[0] = tswap64(regs->xregs[0]);
> +    }
> +
> +    for (i = 1; i < 30; i++) {
> +        gr[i] = tswap64(regs->xregs[i]);
> +    }
> +
> +    mcp->mc_gpregs.gp_sp = tswap64(regs->xregs[TARGET_REG_SP]);
> +    mcp->mc_gpregs.gp_lr = tswap64(regs->xregs[TARGET_REG_LR]);
> +    mcp->mc_gpregs.gp_elr = tswap64(regs->pc);
> +
> +    /* XXX FP? */

Reasonably simple.  See target_setup_fpsimd_record from linux-user/aarch64/signal.c.


r~

Re: [PATCH 21/23] Add setup_sigframe_arch function for ARM AArch64 in bsd-user

[Richard Henderson]

On 6/17/24 11:58, Ajeet Singh wrote:
> From: Warner Losh<imp@bsdimp.com>
> 
> The function utilizes the `get_mcontext` function to retrieve the machine
> context for the current CPUARMState
> 
> Signed-off-by: Warner Losh<imp@bsdimp.com>
> Signed-off-by: Ajeet Singh<itachis@FreeBSD.org>
> ---
>   bsd-user/aarch64/signal.c | 14 ++++++++++++++
>   1 file changed, 14 insertions(+)

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>


r~

Re: [PATCH 22/23] Add set_mcontext function for ARM AArch64 in bsd-user

[Richard Henderson]

On 6/17/24 11:58, Ajeet Singh wrote:
> From: Stacey Son <sson@FreeBSD.org>
> 
> The function copies register values from the provided target_mcontext_t
> structure to the CPUARMState registers
> 
> Signed-off-by: Stacey Son <sson@FreeBSD.org>
> Signed-off-by: Ajeet Singh <itachis@FreeBSD.org>
> ---
>   bsd-user/aarch64/signal.c | 22 ++++++++++++++++++++++
>   1 file changed, 22 insertions(+)
> 
> diff --git a/bsd-user/aarch64/signal.c b/bsd-user/aarch64/signal.c
> index 43c886e603..13faac8ce6 100644
> --- a/bsd-user/aarch64/signal.c
> +++ b/bsd-user/aarch64/signal.c
> @@ -95,3 +95,25 @@ abi_long setup_sigframe_arch(CPUARMState *env, abi_ulong frame_addr,
>       return 0;
>   }
>   
> +/*
> + * Compare to set_mcontext() in arm64/arm64/machdep.c
> + * Assumes that the memory is locked if frame points to user memory.
> + */
> +abi_long set_mcontext(CPUARMState *regs, target_mcontext_t *mcp, int srflag)
> +{
> +    int err = 0, i;
> +    const uint64_t *gr = mcp->mc_gpregs.gp_x;
> +
> +    for (i = 0; i < 30; i++) {
> +        regs->xregs[i] = tswap64(gr[i]);
> +    }
> +
> +    regs->xregs[TARGET_REG_SP] = tswap64(mcp->mc_gpregs.gp_sp);
> +    regs->xregs[TARGET_REG_LR] = tswap64(mcp->mc_gpregs.gp_lr);
> +    regs->pc = mcp->mc_gpregs.gp_elr;

tswap.

> +    pstate_write(regs, mcp->mc_gpregs.gp_spsr);
> +
> +    /* XXX FP? */

Similarly, see target_restore_fpsimd_record.


r~

Re: [PATCH 23/23] Add get_ucontext_sigreturn function

[Richard Henderson]

On 6/17/24 11:58, Ajeet Singh wrote:
> From: Stacey Son <sson@FreeBSD.org>
> 
> Function checks the processor state to ensure that the current
> execution mode is EL0 and no flags indicating interrupts or
> exceptions are set
> 
> Signed-off-by: Stacey Son <sson@FreeBSD.org>
> Signed-off-by: Ajeet Singh <itachis@FreeBSD.org>
> ---
>   bsd-user/aarch64/signal.c | 18 ++++++++++++++++++
>   1 file changed, 18 insertions(+)
> 
> diff --git a/bsd-user/aarch64/signal.c b/bsd-user/aarch64/signal.c
> index 13faac8ce6..ad81531ec5 100644
> --- a/bsd-user/aarch64/signal.c
> +++ b/bsd-user/aarch64/signal.c
> @@ -117,3 +117,21 @@ abi_long set_mcontext(CPUARMState *regs, target_mcontext_t *mcp, int srflag)
>   
>       return err;
>   }
> +
> +/* Compare to sys_sigreturn() in  arm64/arm64/machdep.c */
> +abi_long get_ucontext_sigreturn(CPUARMState *regs, abi_ulong target_sf,
> +                                abi_ulong *target_uc)
> +{
> +    uint32_t pstate = pstate_read(regs);
> +
> +    *target_uc = 0;
> +
> +    if ((pstate & PSTATE_M) != PSTATE_MODE_EL0t  ||
> +        (pstate & (PSTATE_F | PSTATE_I | PSTATE_A | PSTATE_D)) != 0) {
> +        return -TARGET_EINVAL;
> +    }
> +
> +    *target_uc = target_sf;

Why delay this store?  I don't see why you're assigning 0 above.


r~

Re: [PATCH 01/23] Add CPU initialization function

[Warner Losh]

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On Mon, Jun 17, 2024 at 10:17 PM Richard Henderson <
richard.henderson@linaro.org> wrote:

> On 6/17/24 11:57, Ajeet Singh wrote:
> > From: Stacey Son <sson@FreeBSD.org>
> >
> > Addded function to initialize ARM CPU
> > and to check if it supports 64 bit mode
> >
> > Signed-off-by: Ajeet Singh <itachis@FreeBSD.org>
> > Signed-off-by: Stacey Son <sson@FreeBSD.org>
> > ---
> >   bsd-user/aarch64/target_arch_cpu.h | 42 ++++++++++++++++++++++++++++++
> >   1 file changed, 42 insertions(+)
> >   create mode 100644 bsd-user/aarch64/target_arch_cpu.h
> >
> > diff --git a/bsd-user/aarch64/target_arch_cpu.h
> b/bsd-user/aarch64/target_arch_cpu.h
> > new file mode 100644
> > index 0000000000..db5c7062b9
> > --- /dev/null
> > +++ b/bsd-user/aarch64/target_arch_cpu.h
> > @@ -0,0 +1,42 @@
> > +/*
> > + *  ARM AArch64 cpu init and loop
> > + *
> > + * Copyright (c) 2015 Stacey Son
> > + *
> > + * This library is free software; you can redistribute it and/or
> > + * modify it under the terms of the GNU Lesser General Public
> > + * License as published by the Free Software Foundation; either
> > + * version 2 of the License, or (at your option) any later version.
> > + *
> > + * This library is distributed in the hope that it will be useful,
> > + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
> > + * Lesser General Public License for more details.
> > + *
> > + * You should have received a copy of the GNU Lesser General Public
> > + * License along with this library; if not, see <
> http://www.gnu.org/licenses/>.
> > + */
> > +
> > +#ifndef TARGET_ARCH_CPU_H
> > +#define TARGET_ARCH_CPU_H
> > +
> > +#include "target_arch.h"
> > +#include "target/arm/syndrome.h"
>
> Do you actually need syndrome.h?
>

It's needed, but not for this chunk. It is needed for patch 2 because we
start to use the syndrome functions there to dispatch / decode the traps.
So that should be moved to patch 2 in the next round, I think.

Also

Reviewed-by: Warner Losh <imp@bsdimp.com>

since this looks correct and I didn't write it :)

Warner


> Otherwise,
> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
>
> r~
>
> > +
> > +#define TARGET_DEFAULT_CPU_MODEL "any"
> > +
> > +static inline void target_cpu_init(CPUARMState *env,
> > +    struct target_pt_regs *regs)
> > +{
> > +    int i;
> > +
> > +    if (!(arm_feature(env, ARM_FEATURE_AARCH64))) {
> > +        fprintf(stderr, "The selected ARM CPU does not support 64 bit
> mode\n");
> > +        exit(1);
> > +    }
> > +    for (i = 0; i < 31; i++) {
> > +        env->xregs[i] = regs->regs[i];
> > +    }
> > +    env->pc = regs->pc;
> > +    env->xregs[31] = regs->sp;
> > +}
>
>

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Re: [PATCH 02/23] Added CPU loop function

[Warner Losh]

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On Mon, Jun 17, 2024 at 10:24 PM Richard Henderson <
richard.henderson@linaro.org> wrote:

> On 6/17/24 11:57, Ajeet Singh wrote:
> > +            /*
> > +             * The carry bit is cleared for no error; set for error.
> > +             * See arm64/arm64/vm_machdep.c cpu_set_syscall_retval()
> > +             */
> > +            pstate = pstate_read(env);
> > +            if (ret >= 0) {
> > +                pstate &= ~PSTATE_C;
> > +                env->xregs[0] = ret;
> > +            } else if (ret == -TARGET_ERESTART) {
> > +                env->pc -= 4;
> > +                break;
> > +            } else if (ret != -TARGET_EJUSTRETURN) {
> > +                pstate |= PSTATE_C;
> > +                env->xregs[0] = -ret;
> > +            }
> > +            pstate_write(env, pstate);
>
> No need for full pstate read/write:
>
>      env->CF = {0,1};
>

If I understand what you're suggesting, the quoted code can be replaced
by the following, faster construct:

            /*
             * The carry bit is cleared for no error; set for error.
             * See arm64/arm64/vm_machdep.c cpu_set_syscall_retval()
             */
            if (ret >= 0) {
                env->CF = 0;
                env->xregs[0] = ret;
            } else if (ret == -TARGET_ERESTART) {
                env->pc -= 4;
                break;
            } else if (ret != -TARGET_EJUSTRETURN) {
                env->CF = 1;
                env->xregs[0] = -ret;
            }
            break;

Is that what you're saying?


> > +            break;
> > +
> > +        case EXCP_INTERRUPT:
> > +            /* Just indicate that signals should be handle ASAP. */
> > +            break;
> > +
> > +        case EXCP_UDEF:
> > +            force_sig_fault(TARGET_SIGILL, TARGET_ILL_ILLOPN, env->pc);
> > +            break;
> > +
> > +
> > +        case EXCP_PREFETCH_ABORT:
> > +        case EXCP_DATA_ABORT:
> > +            /* We should only arrive here with EC in {DATAABORT,
> INSNABORT}. */
> > +            ec = syn_get_ec(env->exception.syndrome);
>
> Nevermind about my question about syndrome.h vs patch 1.
>

Ah, Since we have to re-roll this patch anyway, maybe moving it is a good
idea?
Honestly, I'm good either way.

Warner


> r~
>

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Re: [PATCH 11/23] Update ARM AArch64 VM parameter definitions for bsd-user

[Warner Losh]

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On Tue, Jun 18, 2024 at 4:16 PM Richard Henderson <
richard.henderson@linaro.org> wrote:

> On 6/17/24 11:57, Ajeet Singh wrote:
> > From: Stacey Son <sson@FreeBSD.org>
> >
> > Defined address spaces for FreeBSD/arm64 and added function for
> > getting stack pointer from CPU and setting a return value.
> >
> > Signed-off-by: Stacey Son <sson@FreeBSD.org>
> > Signed-off-by: Warner Losh <imp@bsdimp.com>
> > Signed-off-by: Ajeet Singh <itachis@FreeBSD.org>
> > Co-authored-by: Sean Bruno <sbruno@freebsd.org>
> > Co-authored-by: Warner Losh <imp@bsdimp.com>
> > ---
> >   bsd-user/aarch64/target_arch_vmparam.h | 68 ++++++++++++++++++++++++++
> >   1 file changed, 68 insertions(+)
> >   create mode 100644 bsd-user/aarch64/target_arch_vmparam.h
>
> Acked-by: Richard Henderson <richard.henderson@linaro.org>
>
> > +                /* KERNBASE - 512 MB */
> > +#define TARGET_VM_MAXUSER_ADDRESS   (0x00007fffff000000ULL - (512 *
> MiB))
> > +#define TARGET_USRSTACK             TARGET_VM_MAXUSER_ADDRESS
>
> I will note that this may conflict with -R reserved_size,
> and is an existing issue with the x86_64 port as well.
>

There are indeed existing issues with address space management. We're
working through
them right now in the blitz branch. We have finally found where the atomic
issues were
coming from and it is <blush> not setting the flag saying we want atomic
ops when creating
the CPU structures (that's a quick summary, I'll post more on this later
when we review it).
So I'd suggest, for the moment, allowing this in and fixing it when we get
those details
ironed out. Does that sound OK?

Warner

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Re: [PATCH 22/23] Add set_mcontext function for ARM AArch64 in bsd-user

[Warner Losh]

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On Tue, Jun 18, 2024 at 4:51 PM Richard Henderson <
richard.henderson@linaro.org> wrote:

> On 6/17/24 11:58, Ajeet Singh wrote:
> > From: Stacey Son <sson@FreeBSD.org>
> >
> > The function copies register values from the provided target_mcontext_t
> > structure to the CPUARMState registers
> >
> > Signed-off-by: Stacey Son <sson@FreeBSD.org>
> > Signed-off-by: Ajeet Singh <itachis@FreeBSD.org>
> > ---
> >   bsd-user/aarch64/signal.c | 22 ++++++++++++++++++++++
> >   1 file changed, 22 insertions(+)
> >
> > diff --git a/bsd-user/aarch64/signal.c b/bsd-user/aarch64/signal.c
> > index 43c886e603..13faac8ce6 100644
> > --- a/bsd-user/aarch64/signal.c
> > +++ b/bsd-user/aarch64/signal.c
> > @@ -95,3 +95,25 @@ abi_long setup_sigframe_arch(CPUARMState *env,
> abi_ulong frame_addr,
> >       return 0;
> >   }
> >
> > +/*
> > + * Compare to set_mcontext() in arm64/arm64/machdep.c
> > + * Assumes that the memory is locked if frame points to user memory.
> > + */
> > +abi_long set_mcontext(CPUARMState *regs, target_mcontext_t *mcp, int
> srflag)
> > +{
> > +    int err = 0, i;
> > +    const uint64_t *gr = mcp->mc_gpregs.gp_x;
> > +
> > +    for (i = 0; i < 30; i++) {
> > +        regs->xregs[i] = tswap64(gr[i]);
> > +    }
> > +
> > +    regs->xregs[TARGET_REG_SP] = tswap64(mcp->mc_gpregs.gp_sp);
> > +    regs->xregs[TARGET_REG_LR] = tswap64(mcp->mc_gpregs.gp_lr);
> > +    regs->pc = mcp->mc_gpregs.gp_elr;
>
> tswap.
>

So "regs->pc = tswap64(mcp->mc_gpregs.gp_elr)"  then?


> > +    pstate_write(regs, mcp->mc_gpregs.gp_spsr);
> > +
> > +    /* XXX FP? */
>
> Similarly, see target_restore_fpsimd_record.
>

Since neither this, nor the get_mcontext is written for FP on upstream yet,
can we do those as a followup commit?

Warner


>
> r~
>

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Re: [PATCH 23/23] Add get_ucontext_sigreturn function

[Warner Losh]

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On Tue, Jun 18, 2024 at 4:56 PM Richard Henderson <
richard.henderson@linaro.org> wrote:

> On 6/17/24 11:58, Ajeet Singh wrote:
> > From: Stacey Son <sson@FreeBSD.org>
> >
> > Function checks the processor state to ensure that the current
> > execution mode is EL0 and no flags indicating interrupts or
> > exceptions are set
> >
> > Signed-off-by: Stacey Son <sson@FreeBSD.org>
> > Signed-off-by: Ajeet Singh <itachis@FreeBSD.org>
> > ---
> >   bsd-user/aarch64/signal.c | 18 ++++++++++++++++++
> >   1 file changed, 18 insertions(+)
> >
> > diff --git a/bsd-user/aarch64/signal.c b/bsd-user/aarch64/signal.c
> > index 13faac8ce6..ad81531ec5 100644
> > --- a/bsd-user/aarch64/signal.c
> > +++ b/bsd-user/aarch64/signal.c
> > @@ -117,3 +117,21 @@ abi_long set_mcontext(CPUARMState *regs,
> target_mcontext_t *mcp, int srflag)
> >
> >       return err;
> >   }
> > +
> > +/* Compare to sys_sigreturn() in  arm64/arm64/machdep.c */
>

This is now in exec_machdep.c and the most relevant bits are set_mcontext()
and sys_sigreturn().


> > +abi_long get_ucontext_sigreturn(CPUARMState *regs, abi_ulong target_sf,
> > +                                abi_ulong *target_uc)
> > +{
> > +    uint32_t pstate = pstate_read(regs);
> > +
> > +    *target_uc = 0;
> > +
> > +    if ((pstate & PSTATE_M) != PSTATE_MODE_EL0t  ||
> > +        (pstate & (PSTATE_F | PSTATE_I | PSTATE_A | PSTATE_D)) != 0) {
> > +        return -TARGET_EINVAL;
> > +    }
> > +
> > +    *target_uc = target_sf;
>
> Why delay this store?  I don't see why you're assigning 0 above.
>

I'm not sure I understand this either....  We don't store anything when
there's an error in the pstate, at least in the kernel code.

Warner

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Re: [PATCH 02/23] Added CPU loop function

[Richard Henderson]

On 6/22/24 11:49, Warner Losh wrote:
> 
> 
> On Mon, Jun 17, 2024 at 10:24 PM Richard Henderson <richard.henderson@linaro.org 
> <mailto:richard.henderson@linaro.org>> wrote:
> 
>     On 6/17/24 11:57, Ajeet Singh wrote:
>      > +            /*
>      > +             * The carry bit is cleared for no error; set for error.
>      > +             * See arm64/arm64/vm_machdep.c cpu_set_syscall_retval()
>      > +             */
>      > +            pstate = pstate_read(env);
>      > +            if (ret >= 0) {
>      > +                pstate &= ~PSTATE_C;
>      > +                env->xregs[0] = ret;
>      > +            } else if (ret == -TARGET_ERESTART) {
>      > +                env->pc -= 4;
>      > +                break;
>      > +            } else if (ret != -TARGET_EJUSTRETURN) {
>      > +                pstate |= PSTATE_C;
>      > +                env->xregs[0] = -ret;
>      > +            }
>      > +            pstate_write(env, pstate);
> 
>     No need for full pstate read/write:
> 
>           env->CF = {0,1};
> 
> 
> If I understand what you're suggesting, the quoted code can be replaced
> by the following, faster construct:
> 
>              /*
>               * The carry bit is cleared for no error; set for error.
>               * See arm64/arm64/vm_machdep.c cpu_set_syscall_retval()
>               */
>              if (ret >= 0) {
>                  env->CF = 0;
>                  env->xregs[0] = ret;
>              } else if (ret == -TARGET_ERESTART) {
>                  env->pc -= 4;
>                  break;
>              } else if (ret != -TARGET_EJUSTRETURN) {
>                  env->CF = 1;
>                  env->xregs[0] = -ret;
>              }
>              break;
> 
> Is that what you're saying?

Yes.

> 
>      > +            break;
>      > +
>      > +        case EXCP_INTERRUPT:
>      > +            /* Just indicate that signals should be handle ASAP. */
>      > +            break;
>      > +
>      > +        case EXCP_UDEF:
>      > +            force_sig_fault(TARGET_SIGILL, TARGET_ILL_ILLOPN, env->pc);
>      > +            break;
>      > +
>      > +
>      > +        case EXCP_PREFETCH_ABORT:
>      > +        case EXCP_DATA_ABORT:
>      > +            /* We should only arrive here with EC in {DATAABORT, INSNABORT}. */
>      > +            ec = syn_get_ec(env->exception.syndrome);
> 
>     Nevermind about my question about syndrome.h vs patch 1.
> 
> 
> Ah, Since we have to re-roll this patch anyway, maybe moving it is a good idea?
> Honestly, I'm good either way.

Least effort is called for.  :-)


r~

Re: [PATCH 22/23] Add set_mcontext function for ARM AArch64 in bsd-user

[Richard Henderson]

On 6/23/24 08:54, Warner Losh wrote:
> 
> 
> On Tue, Jun 18, 2024 at 4:51 PM Richard Henderson <richard.henderson@linaro.org 
> <mailto:richard.henderson@linaro.org>> wrote:
> 
>     On 6/17/24 11:58, Ajeet Singh wrote:
>      > From: Stacey Son <sson@FreeBSD.org>
>      >
>      > The function copies register values from the provided target_mcontext_t
>      > structure to the CPUARMState registers
>      >
>      > Signed-off-by: Stacey Son <sson@FreeBSD.org>
>      > Signed-off-by: Ajeet Singh <itachis@FreeBSD.org>
>      > ---
>      >   bsd-user/aarch64/signal.c | 22 ++++++++++++++++++++++
>      >   1 file changed, 22 insertions(+)
>      >
>      > diff --git a/bsd-user/aarch64/signal.c b/bsd-user/aarch64/signal.c
>      > index 43c886e603..13faac8ce6 100644
>      > --- a/bsd-user/aarch64/signal.c
>      > +++ b/bsd-user/aarch64/signal.c
>      > @@ -95,3 +95,25 @@ abi_long setup_sigframe_arch(CPUARMState *env, abi_ulong frame_addr,
>      >       return 0;
>      >   }
>      >
>      > +/*
>      > + * Compare to set_mcontext() in arm64/arm64/machdep.c
>      > + * Assumes that the memory is locked if frame points to user memory.
>      > + */
>      > +abi_long set_mcontext(CPUARMState *regs, target_mcontext_t *mcp, int srflag)
>      > +{
>      > +    int err = 0, i;
>      > +    const uint64_t *gr = mcp->mc_gpregs.gp_x;
>      > +
>      > +    for (i = 0; i < 30; i++) {
>      > +        regs->xregs[i] = tswap64(gr[i]);
>      > +    }
>      > +
>      > +    regs->xregs[TARGET_REG_SP] = tswap64(mcp->mc_gpregs.gp_sp);
>      > +    regs->xregs[TARGET_REG_LR] = tswap64(mcp->mc_gpregs.gp_lr);
>      > +    regs->pc = mcp->mc_gpregs.gp_elr;
> 
>     tswap.
> 
> 
> So "regs->pc = tswap64(mcp->mc_gpregs.gp_elr)"  then?

Yes.

> 
>      > +    pstate_write(regs, mcp->mc_gpregs.gp_spsr);
>      > +
>      > +    /* XXX FP? */
> 
>     Similarly, see target_restore_fpsimd_record.
> 
> 
> Since neither this, nor the get_mcontext is written for FP on upstream yet, can we do 
> those as a followup commit?

Yes.


r~

Re: [PATCH 06/23] Add Aarch64 register handling

[Warner Losh]

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On Mon, Jun 17, 2024 at 10:35 PM Richard Henderson <
richard.henderson@linaro.org> wrote:

> On 6/17/24 11:57, Ajeet Singh wrote:
> > From: Stacey Son <sson@FreeBSD.org>
> >
> > Header file for managing CPU register states in
> > FreeBSD user mode
> >
> > Signed-off-by: Stacey Son <sson@FreeBSD.org>
> > Signed-off-by: Ajeet Singh <itachis@FreeBSD.org>
> > ---
> >   bsd-user/aarch64/target_arch_reg.h | 56 ++++++++++++++++++++++++++++++
> >   1 file changed, 56 insertions(+)
> >   create mode 100644 bsd-user/aarch64/target_arch_reg.h
> >
> > diff --git a/bsd-user/aarch64/target_arch_reg.h
> b/bsd-user/aarch64/target_arch_reg.h
> > new file mode 100644
> > index 0000000000..5c7154f0c1
> > --- /dev/null
> > +++ b/bsd-user/aarch64/target_arch_reg.h
> > @@ -0,0 +1,56 @@
> > +/*
> > + *  FreeBSD arm64 register structures
> > + *
> > + *  Copyright (c) 2015 Stacey Son
> > + *  All rights reserved.
> > + *
> > + *  This program is free software; you can redistribute it and/or modify
> > + *  it under the terms of the GNU General Public License as published by
> > + *  the Free Software Foundation; either version 2 of the License, or
> > + *  (at your option) any later version.
> > + *
> > + *  This program is distributed in the hope that it will be useful,
> > + *  but WITHOUT ANY WARRANTY; without even the implied warranty of
> > + *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> > + *  GNU General Public License for more details.
> > + *
> > + *  You should have received a copy of the GNU General Public License
> > + *  along with this program; if not, see <http://www.gnu.org/licenses/
> >.
> > + */
> > +
> > +#ifndef TARGET_ARCH_REG_H
> > +#define TARGET_ARCH_REG_H
> > +
> > +/* See sys/arm64/include/reg.h */
> > +typedef struct target_reg {
> > +    uint64_t        x[30];
> > +    uint64_t        lr;
> > +    uint64_t        sp;
> > +    uint64_t        elr;
> > +    uint64_t        spsr;
> > +} target_reg_t;
> > +
> > +typedef struct target_fpreg {
> > +    __uint128_t     fp_q[32];
>
> I'm not keen on this, though possibly it doesn't matter for hosts that
> bsd-user is
> intended to support.  Better as either Int128 or uint64_t fp_q[32][2].
>

OK. We don't use In128 anywhere today, but it's an easy change.


> What is this structure used for within qemu?
>

Yes. target_fpreg_t is used by the generic core dump code. This reserves
the proper amount of space for it. IIRC, gdb gets cranky if you don't, but
that memory is "dim" in my head, so maybe that problem was corrected ages
ago.


> Does freebsd support SVE yet?
>

Yes. But as later patches show bsd-user does not. I need to add that
support. None of our target applications seem to care, but that might just
be because the wrong answers are produced w/o a crash and there's enough
other crashes that it hasn't percolated up to the top of anybody's queue...


> It's certainly not used with this patch, so it's hard to tell, but can we
> omit it entirely
> for now?
>

It will be necessary for the core dump stuff, though I suppose it's all 0's
right now.  And core dumps are a low-priority item, but it just has to be
SOMETHING, so I propose we just change it here (and in
target_arch_signal.h) to be Int128 and then the future set of changes that
will add FP support for signals, etc will make whatever tweaks / fixes are
needed then.

Warner

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Re: [PATCH 12/23] Add ability to get rval2

[Warner Losh]

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On Tue, Jun 18, 2024 at 4:17 PM Richard Henderson <
richard.henderson@linaro.org> wrote:

> On 6/17/24 11:57, Ajeet Singh wrote:
> > From: Warner Losh <imp@bsdimp.com>
> >
> > Function accesses the x1 register which holds the value
> >
> > Signed-off-by: Warner Losh <imp@bsdimp.com>
> > Signed-off-by: Ajeet Singh <itachis@FreeBSD.org>
> > ---
> >   bsd-user/aarch64/target_arch_vmparam.h | 6 ++++++
> >   1 file changed, 6 insertions(+)
> >
> > diff --git a/bsd-user/aarch64/target_arch_vmparam.h
> b/bsd-user/aarch64/target_arch_vmparam.h
> > index dc66e1289b..0c35491970 100644
> > --- a/bsd-user/aarch64/target_arch_vmparam.h
> > +++ b/bsd-user/aarch64/target_arch_vmparam.h
> > @@ -65,4 +65,10 @@ static inline void set_second_rval(CPUARMState
> *state, abi_ulong retval2)
> >   {
> >       state->xregs[1] = retval2; /* XXX not really used on 64-bit arch */
> >   }
> > +
> > +static inline abi_ulong get_second_rval(CPUARMState *state)
> > +{
> > +    return state->xregs[1];
> > +}
>
> The other two ports only define set_second_rval, and this one only defines
> get?  This
> doesn't seem right...
>

The other two ports need to have this added. Upstream, there's some code
that uses this in the system call tracing path.

Warner

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