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From: Richard Henderson <richard.henderson@linaro.org>
To: "Rémi Denis-Courmont" <remi@remlab.net>, qemu-arm@nongnu.org
Cc: qemu-devel@nongnu.org
Subject: Re: [PATCH 2/5] target/arm: MTE user mode disassembly
Date: Fri, 13 Mar 2020 07:54:21 -0700	[thread overview]
Message-ID: <b72a1acc-eec1-376a-0fef-caa55799d517@linaro.org> (raw)
In-Reply-To: <20200313140023.83844-2-remi@remlab.net>

On 3/13/20 7:00 AM, Rémi Denis-Courmont wrote:
> +/* Extract an Allocation Tag from an address */
> +static void gen_extract_tag(TCGv_i64 dest, TCGv_i64 source)
> +{
> +    TCGv_i64 sign = tcg_temp_new_i64();
> +
> +    /* See ARMv8.5-A AllocationTagFromAddress pseudocode */
> +    tcg_gen_extract_i64(sign, source, 55, 1);
> +    tcg_gen_extract_i64(dest, source, 56, 4);
> +    tcg_gen_add_i64(dest, dest, sign);
> +    tcg_gen_andi_i64(dest, dest, 0xf);
> +    tcg_temp_free_i64(sign);
> +}

In addition to everything else, I see that you're working from quite an old
beta version of the memtag spec.

Please grab the most recent Arm ARM, F.a:
https://developer.arm.com/docs/ddi0487/latest

The current version does not really distinguish between logical and physical
tags, so there is no add:

bits(4) AArch64.AllocationTagFromAddress(bits(64) tagged_address)
    return tagged_address<59:56>;


r~


      reply	other threads:[~2020-03-13 14:55 UTC|newest]

Thread overview: 2+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-03-13 14:00 [PATCH 2/5] target/arm: MTE user mode disassembly Rémi Denis-Courmont
2020-03-13 14:54 ` Richard Henderson [this message]

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