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[142.114.143.47]) by smtp.gmail.com with ESMTPSA id s16sm6155855qtq.31.2021.09.14.08.57.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 14 Sep 2021 08:57:39 -0700 (PDT) Message-ID: Subject: Re: SMMU Stage 2 translation in QEMU From: shashi.mallela@linaro.org To: eric.auger@redhat.com, Peter Maydell Date: Tue, 14 Sep 2021 11:57:38 -0400 In-Reply-To: References: <909bcf70ba8d88d485ec0b36371633e54edef81c.camel@linaro.org> Content-Type: text/plain; charset="UTF-8" X-Mailer: Evolution 3.28.5 (3.28.5-16.el8) Mime-Version: 1.0 Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=2607:f8b0:4864:20::82f; envelope-from=shashi.mallela@linaro.org; helo=mail-qt1-x82f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: QEMU Developers Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Hi Eric, On Mon, 2021-09-13 at 10:19 +0200, Eric Auger wrote: > Hi Shashi, > > On 9/10/21 3:32 PM, shashi.mallela@linaro.org wrote: > > So that would be the driver code running in guest OS because i see > > tables being setup by arm-smmu driver code in linux,which is > > similar to > > what happens with ITS(table base addresses programmed in registers > > by > > linux driver). > Stage2 SMMU tables are generally not used today. Only stage 1 is > used, > even with VFIO (with KVM). The stage 2 SMMU capability is required for qemu sbsa reference platform to satisfy the sbsa level 3 acs(arm compliance suite) requirements. > SMMUv3 upstream driver does not support S1+S2 (nested). It only > supports > either S1 or S2. Enabling S2 can be done through VFIO driver, if you > select the VFIO_TYPE1_NESTING_IOMMU IOMMU type. This then calls IOMMU > .enable_nesting = arm_smmu_enable_nesting which sets smmu_domain- > >stage > = ARM_SMMU_DOMAIN_NESTED. But the name is misleading as it actually > forces the use of S2 instead of S1. > > However if you look at QEMU VFIO code, no one uses > VFIO_TYPE1_NESTING_IOMMU. Since the current smmuv3 implementation in qemu advertises only stage 1 support,from the qemu device point of view is the stage 2 support included in the integration effort you mentioned or does it need to be taken up from scratch? > > Note I have worked on 2 stage integration for years, without much > success yet: > [RFC v9 00/29] vSMMUv3/pSMMUv3 2 stage VFIO integration > > [PATCH v15 00/12] SMMUv3 Nested Stage Setup (IOMMU part) > [PATCH v13 00/13] SMMUv3 Nested Stage Setup (VFIO part) > > > Thanks > > Eric > > On Fri, 2021-09-10 at 13:54 +0100, Peter Maydell wrote: > > > On Fri, 10 Sept 2021 at 13:39, wrote: > > > > I am referring to the latter,"purely emulated QEMU with an > > > > emulated > > > > SMMU that handles accesses to emulated devices" > > > In that case, the stage 2 tables are set up by the guest > > > code (running at emulated EL2), just as they would be if > > > it were running on real hardware. > > > > > > -- PMM