* [PATCH v4 1/9] linux-headers: Synchronize linux headers from linux v6.7.0-rc8
2024-01-05 7:57 [PATCH v4 0/9] Add loongarch kvm accel support Tianrui Zhao
@ 2024-01-05 7:57 ` Tianrui Zhao
2024-01-05 7:57 ` [PATCH v4 2/9] target/loongarch: Define some kvm_arch interfaces Tianrui Zhao
` (8 subsequent siblings)
9 siblings, 0 replies; 19+ messages in thread
From: Tianrui Zhao @ 2024-01-05 7:57 UTC (permalink / raw)
To: qemu-devel
Cc: gaosong, maobibo, zhaotianrui, mst, cohuck, pbonzini,
marcandre.lureau, berrange, thuth, philmd, richard.henderson,
peter.maydell, yangxiaojuan
Use the scripts/update-linux-headers.sh to synchronize linux
headers from linux v6.7.0-rc8. We mainly want to add the
loongarch linux headers and then add the loongarch kvm support
based on it.
Signed-off-by: Tianrui Zhao <zhaotianrui@loongson.cn>
Acked-by: Song Gao <gaosong@loongson.cn>
---
include/standard-headers/drm/drm_fourcc.h | 2 +
include/standard-headers/linux/fuse.h | 10 +-
include/standard-headers/linux/pci_regs.h | 24 ++-
include/standard-headers/linux/vhost_types.h | 7 +
.../standard-headers/linux/virtio_config.h | 5 +
include/standard-headers/linux/virtio_pci.h | 11 ++
| 32 ++++
| 14 +-
| 1 +
| 108 +++++++++++
| 1 +
| 5 +
| 4 +
| 4 +
| 4 +
| 4 +
| 4 +
| 12 ++
| 4 +
| 4 +
| 4 +
| 3 +
| 3 +
| 180 +++++++++++++++++-
| 11 ++
| 1 +
| 9 +-
| 9 +-
| 47 +++--
| 8 +
30 files changed, 504 insertions(+), 31 deletions(-)
create mode 100644 linux-headers/asm-loongarch/bitsperlong.h
create mode 100644 linux-headers/asm-loongarch/kvm.h
create mode 100644 linux-headers/asm-loongarch/mman.h
create mode 100644 linux-headers/asm-loongarch/unistd.h
diff --git a/include/standard-headers/drm/drm_fourcc.h b/include/standard-headers/drm/drm_fourcc.h
index 72279f4d25..3afb70160f 100644
--- a/include/standard-headers/drm/drm_fourcc.h
+++ b/include/standard-headers/drm/drm_fourcc.h
@@ -322,6 +322,8 @@ extern "C" {
* index 1 = Cr:Cb plane, [39:0] Cr1:Cb1:Cr0:Cb0 little endian
*/
#define DRM_FORMAT_NV15 fourcc_code('N', 'V', '1', '5') /* 2x2 subsampled Cr:Cb plane */
+#define DRM_FORMAT_NV20 fourcc_code('N', 'V', '2', '0') /* 2x1 subsampled Cr:Cb plane */
+#define DRM_FORMAT_NV30 fourcc_code('N', 'V', '3', '0') /* non-subsampled Cr:Cb plane */
/*
* 2 plane YCbCr MSB aligned
diff --git a/include/standard-headers/linux/fuse.h b/include/standard-headers/linux/fuse.h
index 6b9793842c..fc0dcd10ae 100644
--- a/include/standard-headers/linux/fuse.h
+++ b/include/standard-headers/linux/fuse.h
@@ -209,7 +209,7 @@
* - add FUSE_HAS_EXPIRE_ONLY
*
* 7.39
- * - add FUSE_DIRECT_IO_RELAX
+ * - add FUSE_DIRECT_IO_ALLOW_MMAP
* - add FUSE_STATX and related structures
*/
@@ -405,8 +405,7 @@ struct fuse_file_lock {
* FUSE_CREATE_SUPP_GROUP: add supplementary group info to create, mkdir,
* symlink and mknod (single group that matches parent)
* FUSE_HAS_EXPIRE_ONLY: kernel supports expiry-only entry invalidation
- * FUSE_DIRECT_IO_RELAX: relax restrictions in FOPEN_DIRECT_IO mode, for now
- * allow shared mmap
+ * FUSE_DIRECT_IO_ALLOW_MMAP: allow shared mmap in FOPEN_DIRECT_IO mode.
*/
#define FUSE_ASYNC_READ (1 << 0)
#define FUSE_POSIX_LOCKS (1 << 1)
@@ -445,7 +444,10 @@ struct fuse_file_lock {
#define FUSE_HAS_INODE_DAX (1ULL << 33)
#define FUSE_CREATE_SUPP_GROUP (1ULL << 34)
#define FUSE_HAS_EXPIRE_ONLY (1ULL << 35)
-#define FUSE_DIRECT_IO_RELAX (1ULL << 36)
+#define FUSE_DIRECT_IO_ALLOW_MMAP (1ULL << 36)
+
+/* Obsolete alias for FUSE_DIRECT_IO_ALLOW_MMAP */
+#define FUSE_DIRECT_IO_RELAX FUSE_DIRECT_IO_ALLOW_MMAP
/**
* CUSE INIT request/reply flags
diff --git a/include/standard-headers/linux/pci_regs.h b/include/standard-headers/linux/pci_regs.h
index e5f558d964..a39193213f 100644
--- a/include/standard-headers/linux/pci_regs.h
+++ b/include/standard-headers/linux/pci_regs.h
@@ -80,6 +80,7 @@
#define PCI_HEADER_TYPE_NORMAL 0
#define PCI_HEADER_TYPE_BRIDGE 1
#define PCI_HEADER_TYPE_CARDBUS 2
+#define PCI_HEADER_TYPE_MFD 0x80 /* Multi-Function Device (possible) */
#define PCI_BIST 0x0f /* 8 bits */
#define PCI_BIST_CODE_MASK 0x0f /* Return result */
@@ -637,6 +638,7 @@
#define PCI_EXP_RTCAP 0x1e /* Root Capabilities */
#define PCI_EXP_RTCAP_CRSVIS 0x0001 /* CRS Software Visibility capability */
#define PCI_EXP_RTSTA 0x20 /* Root Status */
+#define PCI_EXP_RTSTA_PME_RQ_ID 0x0000ffff /* PME Requester ID */
#define PCI_EXP_RTSTA_PME 0x00010000 /* PME status */
#define PCI_EXP_RTSTA_PENDING 0x00020000 /* PME pending */
/*
@@ -930,12 +932,13 @@
/* Process Address Space ID */
#define PCI_PASID_CAP 0x04 /* PASID feature register */
-#define PCI_PASID_CAP_EXEC 0x02 /* Exec permissions Supported */
-#define PCI_PASID_CAP_PRIV 0x04 /* Privilege Mode Supported */
+#define PCI_PASID_CAP_EXEC 0x0002 /* Exec permissions Supported */
+#define PCI_PASID_CAP_PRIV 0x0004 /* Privilege Mode Supported */
+#define PCI_PASID_CAP_WIDTH 0x1f00
#define PCI_PASID_CTRL 0x06 /* PASID control register */
-#define PCI_PASID_CTRL_ENABLE 0x01 /* Enable bit */
-#define PCI_PASID_CTRL_EXEC 0x02 /* Exec permissions Enable */
-#define PCI_PASID_CTRL_PRIV 0x04 /* Privilege Mode Enable */
+#define PCI_PASID_CTRL_ENABLE 0x0001 /* Enable bit */
+#define PCI_PASID_CTRL_EXEC 0x0002 /* Exec permissions Enable */
+#define PCI_PASID_CTRL_PRIV 0x0004 /* Privilege Mode Enable */
#define PCI_EXT_CAP_PASID_SIZEOF 8
/* Single Root I/O Virtualization */
@@ -975,6 +978,8 @@
#define PCI_LTR_VALUE_MASK 0x000003ff
#define PCI_LTR_SCALE_MASK 0x00001c00
#define PCI_LTR_SCALE_SHIFT 10
+#define PCI_LTR_NOSNOOP_VALUE 0x03ff0000 /* Max No-Snoop Latency Value */
+#define PCI_LTR_NOSNOOP_SCALE 0x1c000000 /* Scale for Max Value */
#define PCI_EXT_CAP_LTR_SIZEOF 8
/* Access Control Service */
@@ -1042,9 +1047,16 @@
#define PCI_EXP_DPC_STATUS 0x08 /* DPC Status */
#define PCI_EXP_DPC_STATUS_TRIGGER 0x0001 /* Trigger Status */
#define PCI_EXP_DPC_STATUS_TRIGGER_RSN 0x0006 /* Trigger Reason */
+#define PCI_EXP_DPC_STATUS_TRIGGER_RSN_UNCOR 0x0000 /* Uncorrectable error */
+#define PCI_EXP_DPC_STATUS_TRIGGER_RSN_NFE 0x0002 /* Rcvd ERR_NONFATAL */
+#define PCI_EXP_DPC_STATUS_TRIGGER_RSN_FE 0x0004 /* Rcvd ERR_FATAL */
+#define PCI_EXP_DPC_STATUS_TRIGGER_RSN_IN_EXT 0x0006 /* Reason in Trig Reason Extension field */
#define PCI_EXP_DPC_STATUS_INTERRUPT 0x0008 /* Interrupt Status */
#define PCI_EXP_DPC_RP_BUSY 0x0010 /* Root Port Busy */
#define PCI_EXP_DPC_STATUS_TRIGGER_RSN_EXT 0x0060 /* Trig Reason Extension */
+#define PCI_EXP_DPC_STATUS_TRIGGER_RSN_RP_PIO 0x0000 /* RP PIO error */
+#define PCI_EXP_DPC_STATUS_TRIGGER_RSN_SW_TRIGGER 0x0020 /* DPC SW Trigger bit */
+#define PCI_EXP_DPC_RP_PIO_FEP 0x1f00 /* RP PIO First Err Ptr */
#define PCI_EXP_DPC_SOURCE_ID 0x0A /* DPC Source Identifier */
@@ -1088,6 +1100,8 @@
#define PCI_L1SS_CTL1_LTR_L12_TH_VALUE 0x03ff0000 /* LTR_L1.2_THRESHOLD_Value */
#define PCI_L1SS_CTL1_LTR_L12_TH_SCALE 0xe0000000 /* LTR_L1.2_THRESHOLD_Scale */
#define PCI_L1SS_CTL2 0x0c /* Control 2 Register */
+#define PCI_L1SS_CTL2_T_PWR_ON_SCALE 0x00000003 /* T_POWER_ON Scale */
+#define PCI_L1SS_CTL2_T_PWR_ON_VALUE 0x000000f8 /* T_POWER_ON Value */
/* Designated Vendor-Specific (DVSEC, PCI_EXT_CAP_ID_DVSEC) */
#define PCI_DVSEC_HEADER1 0x4 /* Designated Vendor-Specific Header1 */
diff --git a/include/standard-headers/linux/vhost_types.h b/include/standard-headers/linux/vhost_types.h
index 5ad07e134a..fd54044936 100644
--- a/include/standard-headers/linux/vhost_types.h
+++ b/include/standard-headers/linux/vhost_types.h
@@ -185,5 +185,12 @@ struct vhost_vdpa_iova_range {
* DRIVER_OK
*/
#define VHOST_BACKEND_F_ENABLE_AFTER_DRIVER_OK 0x6
+/* Device may expose the virtqueue's descriptor area, driver area and
+ * device area to a different group for ASID binding than where its
+ * buffers may reside. Requires VHOST_BACKEND_F_IOTLB_ASID.
+ */
+#define VHOST_BACKEND_F_DESC_ASID 0x7
+/* IOTLB don't flush memory mapping across device reset */
+#define VHOST_BACKEND_F_IOTLB_PERSIST 0x8
#endif
diff --git a/include/standard-headers/linux/virtio_config.h b/include/standard-headers/linux/virtio_config.h
index 8a7d0dc8b0..bfd1ca643e 100644
--- a/include/standard-headers/linux/virtio_config.h
+++ b/include/standard-headers/linux/virtio_config.h
@@ -103,6 +103,11 @@
*/
#define VIRTIO_F_NOTIFICATION_DATA 38
+/* This feature indicates that the driver uses the data provided by the device
+ * as a virtqueue identifier in available buffer notifications.
+ */
+#define VIRTIO_F_NOTIF_CONFIG_DATA 39
+
/*
* This feature indicates that the driver can reset a queue individually.
*/
diff --git a/include/standard-headers/linux/virtio_pci.h b/include/standard-headers/linux/virtio_pci.h
index be912cfc95..b7fdfd0668 100644
--- a/include/standard-headers/linux/virtio_pci.h
+++ b/include/standard-headers/linux/virtio_pci.h
@@ -166,6 +166,17 @@ struct virtio_pci_common_cfg {
uint32_t queue_used_hi; /* read-write */
};
+/*
+ * Warning: do not use sizeof on this: use offsetofend for
+ * specific fields you need.
+ */
+struct virtio_pci_modern_common_cfg {
+ struct virtio_pci_common_cfg cfg;
+
+ uint16_t queue_notify_data; /* read-write */
+ uint16_t queue_reset; /* read-write */
+};
+
/* Fields in VIRTIO_PCI_CAP_PCI_CFG: */
struct virtio_pci_cfg_cap {
struct virtio_pci_cap cap;
--git a/linux-headers/asm-arm64/kvm.h b/linux-headers/asm-arm64/kvm.h
index 38e5957526..c59ea55cd8 100644
--- a/linux-headers/asm-arm64/kvm.h
+++ b/linux-headers/asm-arm64/kvm.h
@@ -491,6 +491,38 @@ struct kvm_smccc_filter {
#define KVM_HYPERCALL_EXIT_SMC (1U << 0)
#define KVM_HYPERCALL_EXIT_16BIT (1U << 1)
+/*
+ * Get feature ID registers userspace writable mask.
+ *
+ * From DDI0487J.a, D19.2.66 ("ID_AA64MMFR2_EL1, AArch64 Memory Model
+ * Feature Register 2"):
+ *
+ * "The Feature ID space is defined as the System register space in
+ * AArch64 with op0==3, op1=={0, 1, 3}, CRn==0, CRm=={0-7},
+ * op2=={0-7}."
+ *
+ * This covers all currently known R/O registers that indicate
+ * anything useful feature wise, including the ID registers.
+ *
+ * If we ever need to introduce a new range, it will be described as
+ * such in the range field.
+ */
+#define KVM_ARM_FEATURE_ID_RANGE_IDX(op0, op1, crn, crm, op2) \
+ ({ \
+ __u64 __op1 = (op1) & 3; \
+ __op1 -= (__op1 == 3); \
+ (__op1 << 6 | ((crm) & 7) << 3 | (op2)); \
+ })
+
+#define KVM_ARM_FEATURE_ID_RANGE 0
+#define KVM_ARM_FEATURE_ID_RANGE_SIZE (3 * 8 * 8)
+
+struct reg_mask_range {
+ __u64 addr; /* Pointer to mask array */
+ __u32 range; /* Requested range */
+ __u32 reserved[13];
+};
+
#endif
#endif /* __ARM_KVM_H__ */
--git a/linux-headers/asm-generic/unistd.h b/linux-headers/asm-generic/unistd.h
index abe087c53b..756b013fb8 100644
--- a/linux-headers/asm-generic/unistd.h
+++ b/linux-headers/asm-generic/unistd.h
@@ -71,7 +71,7 @@ __SYSCALL(__NR_fremovexattr, sys_fremovexattr)
#define __NR_getcwd 17
__SYSCALL(__NR_getcwd, sys_getcwd)
#define __NR_lookup_dcookie 18
-__SC_COMP(__NR_lookup_dcookie, sys_lookup_dcookie, compat_sys_lookup_dcookie)
+__SYSCALL(__NR_lookup_dcookie, sys_ni_syscall)
#define __NR_eventfd2 19
__SYSCALL(__NR_eventfd2, sys_eventfd2)
#define __NR_epoll_create1 20
@@ -816,15 +816,21 @@ __SYSCALL(__NR_process_mrelease, sys_process_mrelease)
__SYSCALL(__NR_futex_waitv, sys_futex_waitv)
#define __NR_set_mempolicy_home_node 450
__SYSCALL(__NR_set_mempolicy_home_node, sys_set_mempolicy_home_node)
-
#define __NR_cachestat 451
__SYSCALL(__NR_cachestat, sys_cachestat)
-
#define __NR_fchmodat2 452
__SYSCALL(__NR_fchmodat2, sys_fchmodat2)
+#define __NR_map_shadow_stack 453
+__SYSCALL(__NR_map_shadow_stack, sys_map_shadow_stack)
+#define __NR_futex_wake 454
+__SYSCALL(__NR_futex_wake, sys_futex_wake)
+#define __NR_futex_wait 455
+__SYSCALL(__NR_futex_wait, sys_futex_wait)
+#define __NR_futex_requeue 456
+__SYSCALL(__NR_futex_requeue, sys_futex_requeue)
#undef __NR_syscalls
-#define __NR_syscalls 453
+#define __NR_syscalls 457
/*
* 32 bit systems traditionally used different
--git a/linux-headers/asm-loongarch/bitsperlong.h b/linux-headers/asm-loongarch/bitsperlong.h
new file mode 100644
index 0000000000..6dc0bb0c13
--- /dev/null
+++ b/linux-headers/asm-loongarch/bitsperlong.h
@@ -0,0 +1 @@
+#include <asm-generic/bitsperlong.h>
--git a/linux-headers/asm-loongarch/kvm.h b/linux-headers/asm-loongarch/kvm.h
new file mode 100644
index 0000000000..c6ad2ee610
--- /dev/null
+++ b/linux-headers/asm-loongarch/kvm.h
@@ -0,0 +1,108 @@
+/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
+/*
+ * Copyright (C) 2020-2023 Loongson Technology Corporation Limited
+ */
+
+#ifndef __UAPI_ASM_LOONGARCH_KVM_H
+#define __UAPI_ASM_LOONGARCH_KVM_H
+
+#include <linux/types.h>
+
+/*
+ * KVM LoongArch specific structures and definitions.
+ *
+ * Some parts derived from the x86 version of this file.
+ */
+
+#define __KVM_HAVE_READONLY_MEM
+
+#define KVM_COALESCED_MMIO_PAGE_OFFSET 1
+#define KVM_DIRTY_LOG_PAGE_OFFSET 64
+
+/*
+ * for KVM_GET_REGS and KVM_SET_REGS
+ */
+struct kvm_regs {
+ /* out (KVM_GET_REGS) / in (KVM_SET_REGS) */
+ __u64 gpr[32];
+ __u64 pc;
+};
+
+/*
+ * for KVM_GET_FPU and KVM_SET_FPU
+ */
+struct kvm_fpu {
+ __u32 fcsr;
+ __u64 fcc; /* 8x8 */
+ struct kvm_fpureg {
+ __u64 val64[4];
+ } fpr[32];
+};
+
+/*
+ * For LoongArch, we use KVM_SET_ONE_REG and KVM_GET_ONE_REG to access various
+ * registers. The id field is broken down as follows:
+ *
+ * bits[63..52] - As per linux/kvm.h
+ * bits[51..32] - Must be zero.
+ * bits[31..16] - Register set.
+ *
+ * Register set = 0: GP registers from kvm_regs (see definitions below).
+ *
+ * Register set = 1: CSR registers.
+ *
+ * Register set = 2: KVM specific registers (see definitions below).
+ *
+ * Register set = 3: FPU / SIMD registers (see definitions below).
+ *
+ * Other sets registers may be added in the future. Each set would
+ * have its own identifier in bits[31..16].
+ */
+
+#define KVM_REG_LOONGARCH_GPR (KVM_REG_LOONGARCH | 0x00000ULL)
+#define KVM_REG_LOONGARCH_CSR (KVM_REG_LOONGARCH | 0x10000ULL)
+#define KVM_REG_LOONGARCH_KVM (KVM_REG_LOONGARCH | 0x20000ULL)
+#define KVM_REG_LOONGARCH_FPSIMD (KVM_REG_LOONGARCH | 0x30000ULL)
+#define KVM_REG_LOONGARCH_CPUCFG (KVM_REG_LOONGARCH | 0x40000ULL)
+#define KVM_REG_LOONGARCH_MASK (KVM_REG_LOONGARCH | 0x70000ULL)
+#define KVM_CSR_IDX_MASK 0x7fff
+#define KVM_CPUCFG_IDX_MASK 0x7fff
+
+/*
+ * KVM_REG_LOONGARCH_KVM - KVM specific control registers.
+ */
+
+#define KVM_REG_LOONGARCH_COUNTER (KVM_REG_LOONGARCH_KVM | KVM_REG_SIZE_U64 | 1)
+#define KVM_REG_LOONGARCH_VCPU_RESET (KVM_REG_LOONGARCH_KVM | KVM_REG_SIZE_U64 | 2)
+
+#define LOONGARCH_REG_SHIFT 3
+#define LOONGARCH_REG_64(TYPE, REG) (TYPE | KVM_REG_SIZE_U64 | (REG << LOONGARCH_REG_SHIFT))
+#define KVM_IOC_CSRID(REG) LOONGARCH_REG_64(KVM_REG_LOONGARCH_CSR, REG)
+#define KVM_IOC_CPUCFG(REG) LOONGARCH_REG_64(KVM_REG_LOONGARCH_CPUCFG, REG)
+
+struct kvm_debug_exit_arch {
+};
+
+/* for KVM_SET_GUEST_DEBUG */
+struct kvm_guest_debug_arch {
+};
+
+/* definition of registers in kvm_run */
+struct kvm_sync_regs {
+};
+
+/* dummy definition */
+struct kvm_sregs {
+};
+
+struct kvm_iocsr_entry {
+ __u32 addr;
+ __u32 pad;
+ __u64 data;
+};
+
+#define KVM_NR_IRQCHIPS 1
+#define KVM_IRQCHIP_NUM_PINS 64
+#define KVM_MAX_CORES 256
+
+#endif /* __UAPI_ASM_LOONGARCH_KVM_H */
--git a/linux-headers/asm-loongarch/mman.h b/linux-headers/asm-loongarch/mman.h
new file mode 100644
index 0000000000..8eebf89f5a
--- /dev/null
+++ b/linux-headers/asm-loongarch/mman.h
@@ -0,0 +1 @@
+#include <asm-generic/mman.h>
--git a/linux-headers/asm-loongarch/unistd.h b/linux-headers/asm-loongarch/unistd.h
new file mode 100644
index 0000000000..fcb668984f
--- /dev/null
+++ b/linux-headers/asm-loongarch/unistd.h
@@ -0,0 +1,5 @@
+/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
+#define __ARCH_WANT_SYS_CLONE
+#define __ARCH_WANT_SYS_CLONE3
+
+#include <asm-generic/unistd.h>
--git a/linux-headers/asm-mips/unistd_n32.h b/linux-headers/asm-mips/unistd_n32.h
index 46d8500654..994b6f008f 100644
--- a/linux-headers/asm-mips/unistd_n32.h
+++ b/linux-headers/asm-mips/unistd_n32.h
@@ -381,5 +381,9 @@
#define __NR_set_mempolicy_home_node (__NR_Linux + 450)
#define __NR_cachestat (__NR_Linux + 451)
#define __NR_fchmodat2 (__NR_Linux + 452)
+#define __NR_map_shadow_stack (__NR_Linux + 453)
+#define __NR_futex_wake (__NR_Linux + 454)
+#define __NR_futex_wait (__NR_Linux + 455)
+#define __NR_futex_requeue (__NR_Linux + 456)
#endif /* _ASM_UNISTD_N32_H */
--git a/linux-headers/asm-mips/unistd_n64.h b/linux-headers/asm-mips/unistd_n64.h
index c2f7ac673b..41dcf5877a 100644
--- a/linux-headers/asm-mips/unistd_n64.h
+++ b/linux-headers/asm-mips/unistd_n64.h
@@ -357,5 +357,9 @@
#define __NR_set_mempolicy_home_node (__NR_Linux + 450)
#define __NR_cachestat (__NR_Linux + 451)
#define __NR_fchmodat2 (__NR_Linux + 452)
+#define __NR_map_shadow_stack (__NR_Linux + 453)
+#define __NR_futex_wake (__NR_Linux + 454)
+#define __NR_futex_wait (__NR_Linux + 455)
+#define __NR_futex_requeue (__NR_Linux + 456)
#endif /* _ASM_UNISTD_N64_H */
--git a/linux-headers/asm-mips/unistd_o32.h b/linux-headers/asm-mips/unistd_o32.h
index 757c68f2ad..ae9d334d96 100644
--- a/linux-headers/asm-mips/unistd_o32.h
+++ b/linux-headers/asm-mips/unistd_o32.h
@@ -427,5 +427,9 @@
#define __NR_set_mempolicy_home_node (__NR_Linux + 450)
#define __NR_cachestat (__NR_Linux + 451)
#define __NR_fchmodat2 (__NR_Linux + 452)
+#define __NR_map_shadow_stack (__NR_Linux + 453)
+#define __NR_futex_wake (__NR_Linux + 454)
+#define __NR_futex_wait (__NR_Linux + 455)
+#define __NR_futex_requeue (__NR_Linux + 456)
#endif /* _ASM_UNISTD_O32_H */
--git a/linux-headers/asm-powerpc/unistd_32.h b/linux-headers/asm-powerpc/unistd_32.h
index 8ef94bbac1..b9b23d66d7 100644
--- a/linux-headers/asm-powerpc/unistd_32.h
+++ b/linux-headers/asm-powerpc/unistd_32.h
@@ -434,6 +434,10 @@
#define __NR_set_mempolicy_home_node 450
#define __NR_cachestat 451
#define __NR_fchmodat2 452
+#define __NR_map_shadow_stack 453
+#define __NR_futex_wake 454
+#define __NR_futex_wait 455
+#define __NR_futex_requeue 456
#endif /* _ASM_UNISTD_32_H */
--git a/linux-headers/asm-powerpc/unistd_64.h b/linux-headers/asm-powerpc/unistd_64.h
index 0e7ee43e88..cbb4b3e8f7 100644
--- a/linux-headers/asm-powerpc/unistd_64.h
+++ b/linux-headers/asm-powerpc/unistd_64.h
@@ -406,6 +406,10 @@
#define __NR_set_mempolicy_home_node 450
#define __NR_cachestat 451
#define __NR_fchmodat2 452
+#define __NR_map_shadow_stack 453
+#define __NR_futex_wake 454
+#define __NR_futex_wait 455
+#define __NR_futex_requeue 456
#endif /* _ASM_UNISTD_64_H */
--git a/linux-headers/asm-riscv/kvm.h b/linux-headers/asm-riscv/kvm.h
index 992c5e4071..60d3b21dea 100644
--- a/linux-headers/asm-riscv/kvm.h
+++ b/linux-headers/asm-riscv/kvm.h
@@ -80,6 +80,7 @@ struct kvm_riscv_csr {
unsigned long sip;
unsigned long satp;
unsigned long scounteren;
+ unsigned long senvcfg;
};
/* AIA CSR registers for KVM_GET_ONE_REG and KVM_SET_ONE_REG */
@@ -93,6 +94,11 @@ struct kvm_riscv_aia_csr {
unsigned long iprio2h;
};
+/* Smstateen CSR for KVM_GET_ONE_REG and KVM_SET_ONE_REG */
+struct kvm_riscv_smstateen_csr {
+ unsigned long sstateen0;
+};
+
/* TIMER registers for KVM_GET_ONE_REG and KVM_SET_ONE_REG */
struct kvm_riscv_timer {
__u64 frequency;
@@ -131,6 +137,8 @@ enum KVM_RISCV_ISA_EXT_ID {
KVM_RISCV_ISA_EXT_ZICSR,
KVM_RISCV_ISA_EXT_ZIFENCEI,
KVM_RISCV_ISA_EXT_ZIHPM,
+ KVM_RISCV_ISA_EXT_SMSTATEEN,
+ KVM_RISCV_ISA_EXT_ZICOND,
KVM_RISCV_ISA_EXT_MAX,
};
@@ -148,6 +156,7 @@ enum KVM_RISCV_SBI_EXT_ID {
KVM_RISCV_SBI_EXT_PMU,
KVM_RISCV_SBI_EXT_EXPERIMENTAL,
KVM_RISCV_SBI_EXT_VENDOR,
+ KVM_RISCV_SBI_EXT_DBCN,
KVM_RISCV_SBI_EXT_MAX,
};
@@ -178,10 +187,13 @@ enum KVM_RISCV_SBI_EXT_ID {
#define KVM_REG_RISCV_CSR (0x03 << KVM_REG_RISCV_TYPE_SHIFT)
#define KVM_REG_RISCV_CSR_GENERAL (0x0 << KVM_REG_RISCV_SUBTYPE_SHIFT)
#define KVM_REG_RISCV_CSR_AIA (0x1 << KVM_REG_RISCV_SUBTYPE_SHIFT)
+#define KVM_REG_RISCV_CSR_SMSTATEEN (0x2 << KVM_REG_RISCV_SUBTYPE_SHIFT)
#define KVM_REG_RISCV_CSR_REG(name) \
(offsetof(struct kvm_riscv_csr, name) / sizeof(unsigned long))
#define KVM_REG_RISCV_CSR_AIA_REG(name) \
(offsetof(struct kvm_riscv_aia_csr, name) / sizeof(unsigned long))
+#define KVM_REG_RISCV_CSR_SMSTATEEN_REG(name) \
+ (offsetof(struct kvm_riscv_smstateen_csr, name) / sizeof(unsigned long))
/* Timer registers are mapped as type 4 */
#define KVM_REG_RISCV_TIMER (0x04 << KVM_REG_RISCV_TYPE_SHIFT)
--git a/linux-headers/asm-s390/unistd_32.h b/linux-headers/asm-s390/unistd_32.h
index 716fa368ca..c093e6d5f9 100644
--- a/linux-headers/asm-s390/unistd_32.h
+++ b/linux-headers/asm-s390/unistd_32.h
@@ -425,5 +425,9 @@
#define __NR_set_mempolicy_home_node 450
#define __NR_cachestat 451
#define __NR_fchmodat2 452
+#define __NR_map_shadow_stack 453
+#define __NR_futex_wake 454
+#define __NR_futex_wait 455
+#define __NR_futex_requeue 456
#endif /* _ASM_S390_UNISTD_32_H */
--git a/linux-headers/asm-s390/unistd_64.h b/linux-headers/asm-s390/unistd_64.h
index b2a11b1d13..114c0569a4 100644
--- a/linux-headers/asm-s390/unistd_64.h
+++ b/linux-headers/asm-s390/unistd_64.h
@@ -373,5 +373,9 @@
#define __NR_set_mempolicy_home_node 450
#define __NR_cachestat 451
#define __NR_fchmodat2 452
+#define __NR_map_shadow_stack 453
+#define __NR_futex_wake 454
+#define __NR_futex_wait 455
+#define __NR_futex_requeue 456
#endif /* _ASM_S390_UNISTD_64_H */
--git a/linux-headers/asm-x86/unistd_32.h b/linux-headers/asm-x86/unistd_32.h
index d749ad1c24..329649c377 100644
--- a/linux-headers/asm-x86/unistd_32.h
+++ b/linux-headers/asm-x86/unistd_32.h
@@ -443,6 +443,10 @@
#define __NR_set_mempolicy_home_node 450
#define __NR_cachestat 451
#define __NR_fchmodat2 452
+#define __NR_map_shadow_stack 453
+#define __NR_futex_wake 454
+#define __NR_futex_wait 455
+#define __NR_futex_requeue 456
#endif /* _ASM_UNISTD_32_H */
--git a/linux-headers/asm-x86/unistd_64.h b/linux-headers/asm-x86/unistd_64.h
index cea67282eb..4583606ce6 100644
--- a/linux-headers/asm-x86/unistd_64.h
+++ b/linux-headers/asm-x86/unistd_64.h
@@ -366,6 +366,9 @@
#define __NR_cachestat 451
#define __NR_fchmodat2 452
#define __NR_map_shadow_stack 453
+#define __NR_futex_wake 454
+#define __NR_futex_wait 455
+#define __NR_futex_requeue 456
#endif /* _ASM_UNISTD_64_H */
--git a/linux-headers/asm-x86/unistd_x32.h b/linux-headers/asm-x86/unistd_x32.h
index 5b2e79bf4c..146d74d8e4 100644
--- a/linux-headers/asm-x86/unistd_x32.h
+++ b/linux-headers/asm-x86/unistd_x32.h
@@ -318,6 +318,9 @@
#define __NR_set_mempolicy_home_node (__X32_SYSCALL_BIT + 450)
#define __NR_cachestat (__X32_SYSCALL_BIT + 451)
#define __NR_fchmodat2 (__X32_SYSCALL_BIT + 452)
+#define __NR_futex_wake (__X32_SYSCALL_BIT + 454)
+#define __NR_futex_wait (__X32_SYSCALL_BIT + 455)
+#define __NR_futex_requeue (__X32_SYSCALL_BIT + 456)
#define __NR_rt_sigaction (__X32_SYSCALL_BIT + 512)
#define __NR_rt_sigreturn (__X32_SYSCALL_BIT + 513)
#define __NR_ioctl (__X32_SYSCALL_BIT + 514)
--git a/linux-headers/linux/iommufd.h b/linux-headers/linux/iommufd.h
index 218bf7ac98..806d98d09c 100644
--- a/linux-headers/linux/iommufd.h
+++ b/linux-headers/linux/iommufd.h
@@ -47,6 +47,8 @@ enum {
IOMMUFD_CMD_VFIO_IOAS,
IOMMUFD_CMD_HWPT_ALLOC,
IOMMUFD_CMD_GET_HW_INFO,
+ IOMMUFD_CMD_HWPT_SET_DIRTY_TRACKING,
+ IOMMUFD_CMD_HWPT_GET_DIRTY_BITMAP,
};
/**
@@ -347,20 +349,86 @@ struct iommu_vfio_ioas {
};
#define IOMMU_VFIO_IOAS _IO(IOMMUFD_TYPE, IOMMUFD_CMD_VFIO_IOAS)
+/**
+ * enum iommufd_hwpt_alloc_flags - Flags for HWPT allocation
+ * @IOMMU_HWPT_ALLOC_NEST_PARENT: If set, allocate a HWPT that can serve as
+ * the parent HWPT in a nesting configuration.
+ * @IOMMU_HWPT_ALLOC_DIRTY_TRACKING: Dirty tracking support for device IOMMU is
+ * enforced on device attachment
+ */
+enum iommufd_hwpt_alloc_flags {
+ IOMMU_HWPT_ALLOC_NEST_PARENT = 1 << 0,
+ IOMMU_HWPT_ALLOC_DIRTY_TRACKING = 1 << 1,
+};
+
+/**
+ * enum iommu_hwpt_vtd_s1_flags - Intel VT-d stage-1 page table
+ * entry attributes
+ * @IOMMU_VTD_S1_SRE: Supervisor request
+ * @IOMMU_VTD_S1_EAFE: Extended access enable
+ * @IOMMU_VTD_S1_WPE: Write protect enable
+ */
+enum iommu_hwpt_vtd_s1_flags {
+ IOMMU_VTD_S1_SRE = 1 << 0,
+ IOMMU_VTD_S1_EAFE = 1 << 1,
+ IOMMU_VTD_S1_WPE = 1 << 2,
+};
+
+/**
+ * struct iommu_hwpt_vtd_s1 - Intel VT-d stage-1 page table
+ * info (IOMMU_HWPT_DATA_VTD_S1)
+ * @flags: Combination of enum iommu_hwpt_vtd_s1_flags
+ * @pgtbl_addr: The base address of the stage-1 page table.
+ * @addr_width: The address width of the stage-1 page table
+ * @__reserved: Must be 0
+ */
+struct iommu_hwpt_vtd_s1 {
+ __aligned_u64 flags;
+ __aligned_u64 pgtbl_addr;
+ __u32 addr_width;
+ __u32 __reserved;
+};
+
+/**
+ * enum iommu_hwpt_data_type - IOMMU HWPT Data Type
+ * @IOMMU_HWPT_DATA_NONE: no data
+ * @IOMMU_HWPT_DATA_VTD_S1: Intel VT-d stage-1 page table
+ */
+enum iommu_hwpt_data_type {
+ IOMMU_HWPT_DATA_NONE,
+ IOMMU_HWPT_DATA_VTD_S1,
+};
+
/**
* struct iommu_hwpt_alloc - ioctl(IOMMU_HWPT_ALLOC)
* @size: sizeof(struct iommu_hwpt_alloc)
- * @flags: Must be 0
+ * @flags: Combination of enum iommufd_hwpt_alloc_flags
* @dev_id: The device to allocate this HWPT for
- * @pt_id: The IOAS to connect this HWPT to
+ * @pt_id: The IOAS or HWPT to connect this HWPT to
* @out_hwpt_id: The ID of the new HWPT
* @__reserved: Must be 0
+ * @data_type: One of enum iommu_hwpt_data_type
+ * @data_len: Length of the type specific data
+ * @data_uptr: User pointer to the type specific data
*
* Explicitly allocate a hardware page table object. This is the same object
* type that is returned by iommufd_device_attach() and represents the
* underlying iommu driver's iommu_domain kernel object.
*
- * A HWPT will be created with the IOVA mappings from the given IOAS.
+ * A kernel-managed HWPT will be created with the mappings from the given
+ * IOAS via the @pt_id. The @data_type for this allocation must be set to
+ * IOMMU_HWPT_DATA_NONE. The HWPT can be allocated as a parent HWPT for a
+ * nesting configuration by passing IOMMU_HWPT_ALLOC_NEST_PARENT via @flags.
+ *
+ * A user-managed nested HWPT will be created from a given parent HWPT via
+ * @pt_id, in which the parent HWPT must be allocated previously via the
+ * same ioctl from a given IOAS (@pt_id). In this case, the @data_type
+ * must be set to a pre-defined type corresponding to an I/O page table
+ * type supported by the underlying IOMMU hardware.
+ *
+ * If the @data_type is set to IOMMU_HWPT_DATA_NONE, @data_len and
+ * @data_uptr should be zero. Otherwise, both @data_len and @data_uptr
+ * must be given.
*/
struct iommu_hwpt_alloc {
__u32 size;
@@ -369,13 +437,26 @@ struct iommu_hwpt_alloc {
__u32 pt_id;
__u32 out_hwpt_id;
__u32 __reserved;
+ __u32 data_type;
+ __u32 data_len;
+ __aligned_u64 data_uptr;
};
#define IOMMU_HWPT_ALLOC _IO(IOMMUFD_TYPE, IOMMUFD_CMD_HWPT_ALLOC)
+/**
+ * enum iommu_hw_info_vtd_flags - Flags for VT-d hw_info
+ * @IOMMU_HW_INFO_VTD_ERRATA_772415_SPR17: If set, disallow read-only mappings
+ * on a nested_parent domain.
+ * https://www.intel.com/content/www/us/en/content-details/772415/content-details.html
+ */
+enum iommu_hw_info_vtd_flags {
+ IOMMU_HW_INFO_VTD_ERRATA_772415_SPR17 = 1 << 0,
+};
+
/**
* struct iommu_hw_info_vtd - Intel VT-d hardware information
*
- * @flags: Must be 0
+ * @flags: Combination of enum iommu_hw_info_vtd_flags
* @__reserved: Must be 0
*
* @cap_reg: Value of Intel VT-d capability register defined in VT-d spec
@@ -404,6 +485,20 @@ enum iommu_hw_info_type {
IOMMU_HW_INFO_TYPE_INTEL_VTD,
};
+/**
+ * enum iommufd_hw_capabilities
+ * @IOMMU_HW_CAP_DIRTY_TRACKING: IOMMU hardware support for dirty tracking
+ * If available, it means the following APIs
+ * are supported:
+ *
+ * IOMMU_HWPT_GET_DIRTY_BITMAP
+ * IOMMU_HWPT_SET_DIRTY_TRACKING
+ *
+ */
+enum iommufd_hw_capabilities {
+ IOMMU_HW_CAP_DIRTY_TRACKING = 1 << 0,
+};
+
/**
* struct iommu_hw_info - ioctl(IOMMU_GET_HW_INFO)
* @size: sizeof(struct iommu_hw_info)
@@ -415,6 +510,8 @@ enum iommu_hw_info_type {
* the iommu type specific hardware information data
* @out_data_type: Output the iommu hardware info type as defined in the enum
* iommu_hw_info_type.
+ * @out_capabilities: Output the generic iommu capability info type as defined
+ * in the enum iommu_hw_capabilities.
* @__reserved: Must be 0
*
* Query an iommu type specific hardware information data from an iommu behind
@@ -439,6 +536,81 @@ struct iommu_hw_info {
__aligned_u64 data_uptr;
__u32 out_data_type;
__u32 __reserved;
+ __aligned_u64 out_capabilities;
};
#define IOMMU_GET_HW_INFO _IO(IOMMUFD_TYPE, IOMMUFD_CMD_GET_HW_INFO)
+
+/*
+ * enum iommufd_hwpt_set_dirty_tracking_flags - Flags for steering dirty
+ * tracking
+ * @IOMMU_HWPT_DIRTY_TRACKING_ENABLE: Enable dirty tracking
+ */
+enum iommufd_hwpt_set_dirty_tracking_flags {
+ IOMMU_HWPT_DIRTY_TRACKING_ENABLE = 1,
+};
+
+/**
+ * struct iommu_hwpt_set_dirty_tracking - ioctl(IOMMU_HWPT_SET_DIRTY_TRACKING)
+ * @size: sizeof(struct iommu_hwpt_set_dirty_tracking)
+ * @flags: Combination of enum iommufd_hwpt_set_dirty_tracking_flags
+ * @hwpt_id: HW pagetable ID that represents the IOMMU domain
+ * @__reserved: Must be 0
+ *
+ * Toggle dirty tracking on an HW pagetable.
+ */
+struct iommu_hwpt_set_dirty_tracking {
+ __u32 size;
+ __u32 flags;
+ __u32 hwpt_id;
+ __u32 __reserved;
+};
+#define IOMMU_HWPT_SET_DIRTY_TRACKING _IO(IOMMUFD_TYPE, \
+ IOMMUFD_CMD_HWPT_SET_DIRTY_TRACKING)
+
+/**
+ * enum iommufd_hwpt_get_dirty_bitmap_flags - Flags for getting dirty bits
+ * @IOMMU_HWPT_GET_DIRTY_BITMAP_NO_CLEAR: Just read the PTEs without clearing
+ * any dirty bits metadata. This flag
+ * can be passed in the expectation
+ * where the next operation is an unmap
+ * of the same IOVA range.
+ *
+ */
+enum iommufd_hwpt_get_dirty_bitmap_flags {
+ IOMMU_HWPT_GET_DIRTY_BITMAP_NO_CLEAR = 1,
+};
+
+/**
+ * struct iommu_hwpt_get_dirty_bitmap - ioctl(IOMMU_HWPT_GET_DIRTY_BITMAP)
+ * @size: sizeof(struct iommu_hwpt_get_dirty_bitmap)
+ * @hwpt_id: HW pagetable ID that represents the IOMMU domain
+ * @flags: Combination of enum iommufd_hwpt_get_dirty_bitmap_flags
+ * @__reserved: Must be 0
+ * @iova: base IOVA of the bitmap first bit
+ * @length: IOVA range size
+ * @page_size: page size granularity of each bit in the bitmap
+ * @data: bitmap where to set the dirty bits. The bitmap bits each
+ * represent a page_size which you deviate from an arbitrary iova.
+ *
+ * Checking a given IOVA is dirty:
+ *
+ * data[(iova / page_size) / 64] & (1ULL << ((iova / page_size) % 64))
+ *
+ * Walk the IOMMU pagetables for a given IOVA range to return a bitmap
+ * with the dirty IOVAs. In doing so it will also by default clear any
+ * dirty bit metadata set in the IOPTE.
+ */
+struct iommu_hwpt_get_dirty_bitmap {
+ __u32 size;
+ __u32 hwpt_id;
+ __u32 flags;
+ __u32 __reserved;
+ __aligned_u64 iova;
+ __aligned_u64 length;
+ __aligned_u64 page_size;
+ __aligned_u64 data;
+};
+#define IOMMU_HWPT_GET_DIRTY_BITMAP _IO(IOMMUFD_TYPE, \
+ IOMMUFD_CMD_HWPT_GET_DIRTY_BITMAP)
+
#endif
--git a/linux-headers/linux/kvm.h b/linux-headers/linux/kvm.h
index 0d74ee999a..549fea3a97 100644
--- a/linux-headers/linux/kvm.h
+++ b/linux-headers/linux/kvm.h
@@ -264,6 +264,7 @@ struct kvm_xen_exit {
#define KVM_EXIT_RISCV_SBI 35
#define KVM_EXIT_RISCV_CSR 36
#define KVM_EXIT_NOTIFY 37
+#define KVM_EXIT_LOONGARCH_IOCSR 38
/* For KVM_EXIT_INTERNAL_ERROR */
/* Emulate instruction failed. */
@@ -336,6 +337,13 @@ struct kvm_run {
__u32 len;
__u8 is_write;
} mmio;
+ /* KVM_EXIT_LOONGARCH_IOCSR */
+ struct {
+ __u64 phys_addr;
+ __u8 data[8];
+ __u32 len;
+ __u8 is_write;
+ } iocsr_io;
/* KVM_EXIT_HYPERCALL */
struct {
__u64 nr;
@@ -1188,6 +1196,7 @@ struct kvm_ppc_resize_hpt {
#define KVM_CAP_COUNTER_OFFSET 227
#define KVM_CAP_ARM_EAGER_SPLIT_CHUNK_SIZE 228
#define KVM_CAP_ARM_SUPPORTED_BLOCK_SIZES 229
+#define KVM_CAP_ARM_SUPPORTED_REG_MASK_RANGES 230
#ifdef KVM_CAP_IRQ_ROUTING
@@ -1358,6 +1367,7 @@ struct kvm_dirty_tlb {
#define KVM_REG_ARM64 0x6000000000000000ULL
#define KVM_REG_MIPS 0x7000000000000000ULL
#define KVM_REG_RISCV 0x8000000000000000ULL
+#define KVM_REG_LOONGARCH 0x9000000000000000ULL
#define KVM_REG_SIZE_SHIFT 52
#define KVM_REG_SIZE_MASK 0x00f0000000000000ULL
@@ -1558,6 +1568,7 @@ struct kvm_s390_ucas_mapping {
#define KVM_ARM_MTE_COPY_TAGS _IOR(KVMIO, 0xb4, struct kvm_arm_copy_mte_tags)
/* Available with KVM_CAP_COUNTER_OFFSET */
#define KVM_ARM_SET_COUNTER_OFFSET _IOW(KVMIO, 0xb5, struct kvm_arm_counter_offset)
+#define KVM_ARM_GET_REG_WRITABLE_MASKS _IOR(KVMIO, 0xb6, struct reg_mask_range)
/* ioctl for vm fd */
#define KVM_CREATE_DEVICE _IOWR(KVMIO, 0xe0, struct kvm_create_device)
--git a/linux-headers/linux/psp-sev.h b/linux-headers/linux/psp-sev.h
index 12ccb70099..bcb21339ee 100644
--- a/linux-headers/linux/psp-sev.h
+++ b/linux-headers/linux/psp-sev.h
@@ -68,6 +68,7 @@ typedef enum {
SEV_RET_INVALID_PARAM,
SEV_RET_RESOURCE_LIMIT,
SEV_RET_SECURE_DATA_INVALID,
+ SEV_RET_INVALID_KEY = 0x27,
SEV_RET_MAX,
} sev_ret_code;
--git a/linux-headers/linux/stddef.h b/linux-headers/linux/stddef.h
index 9bb07083ac..bf9749dd14 100644
--- a/linux-headers/linux/stddef.h
+++ b/linux-headers/linux/stddef.h
@@ -27,8 +27,13 @@
union { \
struct { MEMBERS } ATTRS; \
struct TAG { MEMBERS } ATTRS NAME; \
- }
+ } ATTRS
+#ifdef __cplusplus
+/* sizeof(struct{}) is 1 in C++, not 0, can't use C version of the macro. */
+#define __DECLARE_FLEX_ARRAY(T, member) \
+ T member[0]
+#else
/**
* __DECLARE_FLEX_ARRAY() - Declare a flexible array usable in a union
*
@@ -49,3 +54,5 @@
#ifndef __counted_by
#define __counted_by(m)
#endif
+
+#endif /* _LINUX_STDDEF_H */
--git a/linux-headers/linux/userfaultfd.h b/linux-headers/linux/userfaultfd.h
index 59978fbaae..953c75feda 100644
--- a/linux-headers/linux/userfaultfd.h
+++ b/linux-headers/linux/userfaultfd.h
@@ -40,7 +40,8 @@
UFFD_FEATURE_EXACT_ADDRESS | \
UFFD_FEATURE_WP_HUGETLBFS_SHMEM | \
UFFD_FEATURE_WP_UNPOPULATED | \
- UFFD_FEATURE_POISON)
+ UFFD_FEATURE_POISON | \
+ UFFD_FEATURE_WP_ASYNC)
#define UFFD_API_IOCTLS \
((__u64)1 << _UFFDIO_REGISTER | \
(__u64)1 << _UFFDIO_UNREGISTER | \
@@ -216,6 +217,11 @@ struct uffdio_api {
* (i.e. empty ptes). This will be the default behavior for shmem
* & hugetlbfs, so this flag only affects anonymous memory behavior
* when userfault write-protection mode is registered.
+ *
+ * UFFD_FEATURE_WP_ASYNC indicates that userfaultfd write-protection
+ * asynchronous mode is supported in which the write fault is
+ * automatically resolved and write-protection is un-set.
+ * It implies UFFD_FEATURE_WP_UNPOPULATED.
*/
#define UFFD_FEATURE_PAGEFAULT_FLAG_WP (1<<0)
#define UFFD_FEATURE_EVENT_FORK (1<<1)
@@ -232,6 +238,7 @@ struct uffdio_api {
#define UFFD_FEATURE_WP_HUGETLBFS_SHMEM (1<<12)
#define UFFD_FEATURE_WP_UNPOPULATED (1<<13)
#define UFFD_FEATURE_POISON (1<<14)
+#define UFFD_FEATURE_WP_ASYNC (1<<15)
__u64 features;
__u64 ioctls;
--git a/linux-headers/linux/vfio.h b/linux-headers/linux/vfio.h
index acf72b4999..8e175ece31 100644
--- a/linux-headers/linux/vfio.h
+++ b/linux-headers/linux/vfio.h
@@ -277,8 +277,8 @@ struct vfio_region_info {
#define VFIO_REGION_INFO_FLAG_CAPS (1 << 3) /* Info supports caps */
__u32 index; /* Region index */
__u32 cap_offset; /* Offset within info struct of first cap */
- __u64 size; /* Region size (bytes) */
- __u64 offset; /* Region offset from start of device fd */
+ __aligned_u64 size; /* Region size (bytes) */
+ __aligned_u64 offset; /* Region offset from start of device fd */
};
#define VFIO_DEVICE_GET_REGION_INFO _IO(VFIO_TYPE, VFIO_BASE + 8)
@@ -294,8 +294,8 @@ struct vfio_region_info {
#define VFIO_REGION_INFO_CAP_SPARSE_MMAP 1
struct vfio_region_sparse_mmap_area {
- __u64 offset; /* Offset of mmap'able area within region */
- __u64 size; /* Size of mmap'able area */
+ __aligned_u64 offset; /* Offset of mmap'able area within region */
+ __aligned_u64 size; /* Size of mmap'able area */
};
struct vfio_region_info_cap_sparse_mmap {
@@ -450,9 +450,9 @@ struct vfio_device_migration_info {
VFIO_DEVICE_STATE_V1_RESUMING)
__u32 reserved;
- __u64 pending_bytes;
- __u64 data_offset;
- __u64 data_size;
+ __aligned_u64 pending_bytes;
+ __aligned_u64 data_offset;
+ __aligned_u64 data_size;
};
/*
@@ -476,7 +476,7 @@ struct vfio_device_migration_info {
struct vfio_region_info_cap_nvlink2_ssatgt {
struct vfio_info_cap_header header;
- __u64 tgt;
+ __aligned_u64 tgt;
};
/*
@@ -816,7 +816,7 @@ struct vfio_device_gfx_plane_info {
__u32 drm_plane_type; /* type of plane: DRM_PLANE_TYPE_* */
/* out */
__u32 drm_format; /* drm format of plane */
- __u64 drm_format_mod; /* tiled mode */
+ __aligned_u64 drm_format_mod; /* tiled mode */
__u32 width; /* width of plane */
__u32 height; /* height of plane */
__u32 stride; /* stride of plane */
@@ -829,6 +829,7 @@ struct vfio_device_gfx_plane_info {
__u32 region_index; /* region index */
__u32 dmabuf_id; /* dma-buf id */
};
+ __u32 reserved;
};
#define VFIO_DEVICE_QUERY_GFX_PLANE _IO(VFIO_TYPE, VFIO_BASE + 14)
@@ -863,9 +864,10 @@ struct vfio_device_ioeventfd {
#define VFIO_DEVICE_IOEVENTFD_32 (1 << 2) /* 4-byte write */
#define VFIO_DEVICE_IOEVENTFD_64 (1 << 3) /* 8-byte write */
#define VFIO_DEVICE_IOEVENTFD_SIZE_MASK (0xf)
- __u64 offset; /* device fd offset of write */
- __u64 data; /* data to be written */
+ __aligned_u64 offset; /* device fd offset of write */
+ __aligned_u64 data; /* data to be written */
__s32 fd; /* -1 for de-assignment */
+ __u32 reserved;
};
#define VFIO_DEVICE_IOEVENTFD _IO(VFIO_TYPE, VFIO_BASE + 16)
@@ -1434,6 +1436,27 @@ struct vfio_device_feature_mig_data_size {
#define VFIO_DEVICE_FEATURE_MIG_DATA_SIZE 9
+/**
+ * Upon VFIO_DEVICE_FEATURE_SET, set or clear the BUS mastering for the device
+ * based on the operation specified in op flag.
+ *
+ * The functionality is incorporated for devices that needs bus master control,
+ * but the in-band device interface lacks the support. Consequently, it is not
+ * applicable to PCI devices, as bus master control for PCI devices is managed
+ * in-band through the configuration space. At present, this feature is supported
+ * only for CDX devices.
+ * When the device's BUS MASTER setting is configured as CLEAR, it will result in
+ * blocking all incoming DMA requests from the device. On the other hand, configuring
+ * the device's BUS MASTER setting as SET (enable) will grant the device the
+ * capability to perform DMA to the host memory.
+ */
+struct vfio_device_feature_bus_master {
+ __u32 op;
+#define VFIO_DEVICE_FEATURE_CLEAR_MASTER 0 /* Clear Bus Master */
+#define VFIO_DEVICE_FEATURE_SET_MASTER 1 /* Set Bus Master */
+};
+#define VFIO_DEVICE_FEATURE_BUS_MASTER 10
+
/* -------- API for Type1 VFIO IOMMU -------- */
/**
@@ -1449,7 +1472,7 @@ struct vfio_iommu_type1_info {
__u32 flags;
#define VFIO_IOMMU_INFO_PGSIZES (1 << 0) /* supported page sizes info */
#define VFIO_IOMMU_INFO_CAPS (1 << 1) /* Info supports caps */
- __u64 iova_pgsizes; /* Bitmap of supported page sizes */
+ __aligned_u64 iova_pgsizes; /* Bitmap of supported page sizes */
__u32 cap_offset; /* Offset within info struct of first cap */
__u32 pad;
};
--git a/linux-headers/linux/vhost.h b/linux-headers/linux/vhost.h
index f5c48b61ab..649560c685 100644
--- a/linux-headers/linux/vhost.h
+++ b/linux-headers/linux/vhost.h
@@ -219,4 +219,12 @@
*/
#define VHOST_VDPA_RESUME _IO(VHOST_VIRTIO, 0x7E)
+/* Get the group for the descriptor table including driver & device areas
+ * of a virtqueue: read index, write group in num.
+ * The virtqueue index is stored in the index field of vhost_vring_state.
+ * The group ID of the descriptor table for this specific virtqueue
+ * is returned via num field of vhost_vring_state.
+ */
+#define VHOST_VDPA_GET_VRING_DESC_GROUP _IOWR(VHOST_VIRTIO, 0x7F, \
+ struct vhost_vring_state)
#endif
--
2.39.1
^ permalink raw reply related [flat|nested] 19+ messages in thread* [PATCH v4 2/9] target/loongarch: Define some kvm_arch interfaces
2024-01-05 7:57 [PATCH v4 0/9] Add loongarch kvm accel support Tianrui Zhao
2024-01-05 7:57 ` [PATCH v4 1/9] linux-headers: Synchronize linux headers from linux v6.7.0-rc8 Tianrui Zhao
@ 2024-01-05 7:57 ` Tianrui Zhao
2024-01-05 7:57 ` [PATCH v4 3/9] target/loongarch: Supplement vcpu env initial when vcpu reset Tianrui Zhao
` (7 subsequent siblings)
9 siblings, 0 replies; 19+ messages in thread
From: Tianrui Zhao @ 2024-01-05 7:57 UTC (permalink / raw)
To: qemu-devel
Cc: gaosong, maobibo, zhaotianrui, mst, cohuck, pbonzini,
marcandre.lureau, berrange, thuth, philmd, richard.henderson,
peter.maydell, yangxiaojuan, xianglai li
Define some functions in target/loongarch/kvm/kvm.c,
such as kvm_arch_put_registers, kvm_arch_get_registers
and kvm_arch_handle_exit, etc. which are needed by
kvm/kvm-all.c. Now the most functions has no content
and they will be implemented in the next patches.
Signed-off-by: Tianrui Zhao <zhaotianrui@loongson.cn>
Signed-off-by: xianglai li <lixianglai@loongson.cn>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Song Gao <gaosong@loongson.cn>
---
target/loongarch/kvm/kvm.c | 131 +++++++++++++++++++++++++++++++++++++
1 file changed, 131 insertions(+)
create mode 100644 target/loongarch/kvm/kvm.c
diff --git a/target/loongarch/kvm/kvm.c b/target/loongarch/kvm/kvm.c
new file mode 100644
index 0000000000..0d67322fd9
--- /dev/null
+++ b/target/loongarch/kvm/kvm.c
@@ -0,0 +1,131 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/*
+ * QEMU LoongArch KVM
+ *
+ * Copyright (c) 2023 Loongson Technology Corporation Limited
+ */
+
+#include "qemu/osdep.h"
+#include <sys/ioctl.h>
+#include <linux/kvm.h>
+
+#include "qemu/timer.h"
+#include "qemu/error-report.h"
+#include "qemu/main-loop.h"
+#include "sysemu/sysemu.h"
+#include "sysemu/kvm.h"
+#include "sysemu/kvm_int.h"
+#include "hw/pci/pci.h"
+#include "exec/memattrs.h"
+#include "exec/address-spaces.h"
+#include "hw/boards.h"
+#include "hw/irq.h"
+#include "qemu/log.h"
+#include "hw/loader.h"
+#include "migration/migration.h"
+#include "sysemu/runstate.h"
+#include "cpu-csr.h"
+#include "kvm_loongarch.h"
+
+static bool cap_has_mp_state;
+const KVMCapabilityInfo kvm_arch_required_capabilities[] = {
+ KVM_CAP_LAST_INFO
+};
+
+int kvm_arch_get_registers(CPUState *cs)
+{
+ return 0;
+}
+int kvm_arch_put_registers(CPUState *cs, int level)
+{
+ return 0;
+}
+
+int kvm_arch_init_vcpu(CPUState *cs)
+{
+ return 0;
+}
+
+int kvm_arch_destroy_vcpu(CPUState *cs)
+{
+ return 0;
+}
+
+unsigned long kvm_arch_vcpu_id(CPUState *cs)
+{
+ return cs->cpu_index;
+}
+
+int kvm_arch_release_virq_post(int virq)
+{
+ return 0;
+}
+
+int kvm_arch_msi_data_to_gsi(uint32_t data)
+{
+ abort();
+}
+
+int kvm_arch_fixup_msi_route(struct kvm_irq_routing_entry *route,
+ uint64_t address, uint32_t data, PCIDevice *dev)
+{
+ return 0;
+}
+
+int kvm_arch_add_msi_route_post(struct kvm_irq_routing_entry *route,
+ int vector, PCIDevice *dev)
+{
+ return 0;
+}
+
+void kvm_arch_init_irq_routing(KVMState *s)
+{
+}
+
+int kvm_arch_get_default_type(MachineState *ms)
+{
+ return 0;
+}
+
+int kvm_arch_init(MachineState *ms, KVMState *s)
+{
+ return 0;
+}
+
+int kvm_arch_irqchip_create(KVMState *s)
+{
+ return 0;
+}
+
+void kvm_arch_pre_run(CPUState *cs, struct kvm_run *run)
+{
+}
+
+MemTxAttrs kvm_arch_post_run(CPUState *cs, struct kvm_run *run)
+{
+ return MEMTXATTRS_UNSPECIFIED;
+}
+
+int kvm_arch_process_async_events(CPUState *cs)
+{
+ return cs->halted;
+}
+
+bool kvm_arch_stop_on_emulation_error(CPUState *cs)
+{
+ return true;
+}
+
+bool kvm_arch_cpu_check_are_resettable(void)
+{
+ return true;
+}
+
+int kvm_arch_handle_exit(CPUState *cs, struct kvm_run *run)
+{
+ return 0;
+}
+
+void kvm_arch_accel_class_init(ObjectClass *oc)
+{
+}
--
2.39.1
^ permalink raw reply related [flat|nested] 19+ messages in thread* [PATCH v4 3/9] target/loongarch: Supplement vcpu env initial when vcpu reset
2024-01-05 7:57 [PATCH v4 0/9] Add loongarch kvm accel support Tianrui Zhao
2024-01-05 7:57 ` [PATCH v4 1/9] linux-headers: Synchronize linux headers from linux v6.7.0-rc8 Tianrui Zhao
2024-01-05 7:57 ` [PATCH v4 2/9] target/loongarch: Define some kvm_arch interfaces Tianrui Zhao
@ 2024-01-05 7:57 ` Tianrui Zhao
2024-01-05 7:57 ` [PATCH v4 4/9] target/loongarch: Implement kvm get/set registers Tianrui Zhao
` (6 subsequent siblings)
9 siblings, 0 replies; 19+ messages in thread
From: Tianrui Zhao @ 2024-01-05 7:57 UTC (permalink / raw)
To: qemu-devel
Cc: gaosong, maobibo, zhaotianrui, mst, cohuck, pbonzini,
marcandre.lureau, berrange, thuth, philmd, richard.henderson,
peter.maydell, yangxiaojuan, xianglai li
Supplement vcpu env initial when vcpu reset, including
init vcpu CSR_CPUID,CSR_TID to cpu->cpu_index. The two
regs will be used in kvm_get/set_csr_ioctl.
Signed-off-by: Tianrui Zhao <zhaotianrui@loongson.cn>
Signed-off-by: xianglai li <lixianglai@loongson.cn>
Reviewed-by: Song Gao <gaosong@loongson.cn>
---
target/loongarch/cpu.c | 2 ++
target/loongarch/cpu.h | 2 +-
2 files changed, 3 insertions(+), 1 deletion(-)
diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c
index 07319d6fb9..72b83e49aa 100644
--- a/target/loongarch/cpu.c
+++ b/target/loongarch/cpu.c
@@ -533,10 +533,12 @@ static void loongarch_cpu_reset_hold(Object *obj)
env->CSR_ESTAT = env->CSR_ESTAT & (~MAKE_64BIT_MASK(0, 2));
env->CSR_RVACFG = FIELD_DP64(env->CSR_RVACFG, CSR_RVACFG, RBITS, 0);
+ env->CSR_CPUID = cs->cpu_index;
env->CSR_TCFG = FIELD_DP64(env->CSR_TCFG, CSR_TCFG, EN, 0);
env->CSR_LLBCTL = FIELD_DP64(env->CSR_LLBCTL, CSR_LLBCTL, KLO, 0);
env->CSR_TLBRERA = FIELD_DP64(env->CSR_TLBRERA, CSR_TLBRERA, ISTLBR, 0);
env->CSR_MERRCTL = FIELD_DP64(env->CSR_MERRCTL, CSR_MERRCTL, ISMERR, 0);
+ env->CSR_TID = cs->cpu_index;
env->CSR_PRCFG3 = FIELD_DP64(env->CSR_PRCFG3, CSR_PRCFG3, TLB_TYPE, 2);
env->CSR_PRCFG3 = FIELD_DP64(env->CSR_PRCFG3, CSR_PRCFG3, MTLB_ENTRY, 63);
diff --git a/target/loongarch/cpu.h b/target/loongarch/cpu.h
index 00d1fba597..f6d5ef0852 100644
--- a/target/loongarch/cpu.h
+++ b/target/loongarch/cpu.h
@@ -319,6 +319,7 @@ typedef struct CPUArchState {
uint64_t CSR_PWCH;
uint64_t CSR_STLBPS;
uint64_t CSR_RVACFG;
+ uint64_t CSR_CPUID;
uint64_t CSR_PRCFG1;
uint64_t CSR_PRCFG2;
uint64_t CSR_PRCFG3;
@@ -350,7 +351,6 @@ typedef struct CPUArchState {
uint64_t CSR_DBG;
uint64_t CSR_DERA;
uint64_t CSR_DSAVE;
- uint64_t CSR_CPUID;
#ifndef CONFIG_USER_ONLY
LoongArchTLB tlb[LOONGARCH_TLB_MAX];
--
2.39.1
^ permalink raw reply related [flat|nested] 19+ messages in thread* [PATCH v4 4/9] target/loongarch: Implement kvm get/set registers
2024-01-05 7:57 [PATCH v4 0/9] Add loongarch kvm accel support Tianrui Zhao
` (2 preceding siblings ...)
2024-01-05 7:57 ` [PATCH v4 3/9] target/loongarch: Supplement vcpu env initial when vcpu reset Tianrui Zhao
@ 2024-01-05 7:57 ` Tianrui Zhao
2024-01-05 7:58 ` [PATCH v4 5/9] target/loongarch: Implement kvm_arch_init function Tianrui Zhao
` (5 subsequent siblings)
9 siblings, 0 replies; 19+ messages in thread
From: Tianrui Zhao @ 2024-01-05 7:57 UTC (permalink / raw)
To: qemu-devel
Cc: gaosong, maobibo, zhaotianrui, mst, cohuck, pbonzini,
marcandre.lureau, berrange, thuth, philmd, richard.henderson,
peter.maydell, yangxiaojuan, xianglai li
Implement kvm_arch_get/set_registers interfaces, many regs
can be get/set in the function, such as core regs, csr regs,
fpu regs, mp state, etc.
Signed-off-by: Tianrui Zhao <zhaotianrui@loongson.cn>
Signed-off-by: xianglai li <lixianglai@loongson.cn>
Reviewed-by: Song Gao <gaosong@loongson.cn>
Change-Id: Ia8fc48fe08b1768853f7729e77d37cdf270031e4
---
meson.build | 1 +
target/loongarch/cpu.c | 3 +
target/loongarch/cpu.h | 1 +
target/loongarch/internals.h | 5 +-
target/loongarch/kvm/kvm.c | 580 +++++++++++++++++++++++++++++++++-
target/loongarch/trace-events | 11 +
target/loongarch/trace.h | 1 +
7 files changed, 599 insertions(+), 3 deletions(-)
create mode 100644 target/loongarch/trace-events
create mode 100644 target/loongarch/trace.h
diff --git a/meson.build b/meson.build
index 6c77d9687d..445f2b7c2b 100644
--- a/meson.build
+++ b/meson.build
@@ -3358,6 +3358,7 @@ if have_system or have_user
'target/hppa',
'target/i386',
'target/i386/kvm',
+ 'target/loongarch',
'target/mips/tcg',
'target/nios2',
'target/ppc',
diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c
index 72b83e49aa..6614a094c8 100644
--- a/target/loongarch/cpu.c
+++ b/target/loongarch/cpu.c
@@ -555,6 +555,9 @@ static void loongarch_cpu_reset_hold(Object *obj)
#ifndef CONFIG_USER_ONLY
env->pc = 0x1c000000;
memset(env->tlb, 0, sizeof(env->tlb));
+ if (kvm_enabled()) {
+ kvm_arch_reset_vcpu(env);
+ }
#endif
restore_fp_status(env);
diff --git a/target/loongarch/cpu.h b/target/loongarch/cpu.h
index f6d5ef0852..f4a89bd626 100644
--- a/target/loongarch/cpu.h
+++ b/target/loongarch/cpu.h
@@ -360,6 +360,7 @@ typedef struct CPUArchState {
MemoryRegion iocsr_mem;
bool load_elf;
uint64_t elf_address;
+ uint32_t mp_state;
/* Store ipistate to access from this struct */
DeviceState *ipistate;
#endif
diff --git a/target/loongarch/internals.h b/target/loongarch/internals.h
index c492863cc5..0beb034748 100644
--- a/target/loongarch/internals.h
+++ b/target/loongarch/internals.h
@@ -31,8 +31,10 @@ void G_NORETURN do_raise_exception(CPULoongArchState *env,
const char *loongarch_exception_name(int32_t exception);
+#ifdef CONFIG_TCG
int ieee_ex_to_loongarch(int xcpt);
void restore_fp_status(CPULoongArchState *env);
+#endif
#ifndef CONFIG_USER_ONLY
extern const VMStateDescription vmstate_loongarch_cpu;
@@ -44,12 +46,13 @@ uint64_t cpu_loongarch_get_constant_timer_counter(LoongArchCPU *cpu);
uint64_t cpu_loongarch_get_constant_timer_ticks(LoongArchCPU *cpu);
void cpu_loongarch_store_constant_timer_config(LoongArchCPU *cpu,
uint64_t value);
-
+#ifdef CONFIG_TCG
bool loongarch_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
MMUAccessType access_type, int mmu_idx,
bool probe, uintptr_t retaddr);
hwaddr loongarch_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
+#endif
#endif /* !CONFIG_USER_ONLY */
uint64_t read_fcc(CPULoongArchState *env);
diff --git a/target/loongarch/kvm/kvm.c b/target/loongarch/kvm/kvm.c
index 0d67322fd9..e7c9ef830c 100644
--- a/target/loongarch/kvm/kvm.c
+++ b/target/loongarch/kvm/kvm.c
@@ -26,19 +26,595 @@
#include "sysemu/runstate.h"
#include "cpu-csr.h"
#include "kvm_loongarch.h"
+#include "trace.h"
static bool cap_has_mp_state;
const KVMCapabilityInfo kvm_arch_required_capabilities[] = {
KVM_CAP_LAST_INFO
};
+static int kvm_loongarch_get_regs_core(CPUState *cs)
+{
+ int ret = 0;
+ int i;
+ struct kvm_regs regs;
+ LoongArchCPU *cpu = LOONGARCH_CPU(cs);
+ CPULoongArchState *env = &cpu->env;
+
+ /* Get the current register set as KVM seems it */
+ ret = kvm_vcpu_ioctl(cs, KVM_GET_REGS, ®s);
+ if (ret < 0) {
+ trace_kvm_failed_get_regs_core(strerror(errno));
+ return ret;
+ }
+ /* gpr[0] value is always 0 */
+ env->gpr[0] = 0;
+ for (i = 1; i < 32; i++) {
+ env->gpr[i] = regs.gpr[i];
+ }
+
+ env->pc = regs.pc;
+ return ret;
+}
+
+static int kvm_loongarch_put_regs_core(CPUState *cs)
+{
+ int ret = 0;
+ int i;
+ struct kvm_regs regs;
+ LoongArchCPU *cpu = LOONGARCH_CPU(cs);
+ CPULoongArchState *env = &cpu->env;
+
+ /* Set the registers based on QEMU's view of things */
+ for (i = 0; i < 32; i++) {
+ regs.gpr[i] = env->gpr[i];
+ }
+
+ regs.pc = env->pc;
+ ret = kvm_vcpu_ioctl(cs, KVM_SET_REGS, ®s);
+ if (ret < 0) {
+ trace_kvm_failed_put_regs_core(strerror(errno));
+ }
+
+ return ret;
+}
+
+static int kvm_loongarch_get_csr(CPUState *cs)
+{
+ int ret = 0;
+ LoongArchCPU *cpu = LOONGARCH_CPU(cs);
+ CPULoongArchState *env = &cpu->env;
+
+ ret |= kvm_get_one_reg(cs, KVM_IOC_CSRID(LOONGARCH_CSR_CRMD),
+ &env->CSR_CRMD);
+
+ ret |= kvm_get_one_reg(cs, KVM_IOC_CSRID(LOONGARCH_CSR_PRMD),
+ &env->CSR_PRMD);
+
+ ret |= kvm_get_one_reg(cs, KVM_IOC_CSRID(LOONGARCH_CSR_EUEN),
+ &env->CSR_EUEN);
+
+ ret |= kvm_get_one_reg(cs, KVM_IOC_CSRID(LOONGARCH_CSR_MISC),
+ &env->CSR_MISC);
+
+ ret |= kvm_get_one_reg(cs, KVM_IOC_CSRID(LOONGARCH_CSR_ECFG),
+ &env->CSR_ECFG);
+
+ ret |= kvm_get_one_reg(cs, KVM_IOC_CSRID(LOONGARCH_CSR_ESTAT),
+ &env->CSR_ESTAT);
+
+ ret |= kvm_get_one_reg(cs, KVM_IOC_CSRID(LOONGARCH_CSR_ERA),
+ &env->CSR_ERA);
+
+ ret |= kvm_get_one_reg(cs, KVM_IOC_CSRID(LOONGARCH_CSR_BADV),
+ &env->CSR_BADV);
+
+ ret |= kvm_get_one_reg(cs, KVM_IOC_CSRID(LOONGARCH_CSR_BADI),
+ &env->CSR_BADI);
+
+ ret |= kvm_get_one_reg(cs, KVM_IOC_CSRID(LOONGARCH_CSR_EENTRY),
+ &env->CSR_EENTRY);
+
+ ret |= kvm_get_one_reg(cs, KVM_IOC_CSRID(LOONGARCH_CSR_TLBIDX),
+ &env->CSR_TLBIDX);
+
+ ret |= kvm_get_one_reg(cs, KVM_IOC_CSRID(LOONGARCH_CSR_TLBEHI),
+ &env->CSR_TLBEHI);
+
+ ret |= kvm_get_one_reg(cs, KVM_IOC_CSRID(LOONGARCH_CSR_TLBELO0),
+ &env->CSR_TLBELO0);
+
+ ret |= kvm_get_one_reg(cs, KVM_IOC_CSRID(LOONGARCH_CSR_TLBELO1),
+ &env->CSR_TLBELO1);
+
+ ret |= kvm_get_one_reg(cs, KVM_IOC_CSRID(LOONGARCH_CSR_ASID),
+ &env->CSR_ASID);
+
+ ret |= kvm_get_one_reg(cs, KVM_IOC_CSRID(LOONGARCH_CSR_PGDL),
+ &env->CSR_PGDL);
+
+ ret |= kvm_get_one_reg(cs, KVM_IOC_CSRID(LOONGARCH_CSR_PGDH),
+ &env->CSR_PGDH);
+
+ ret |= kvm_get_one_reg(cs, KVM_IOC_CSRID(LOONGARCH_CSR_PGD),
+ &env->CSR_PGD);
+
+ ret |= kvm_get_one_reg(cs, KVM_IOC_CSRID(LOONGARCH_CSR_PWCL),
+ &env->CSR_PWCL);
+
+ ret |= kvm_get_one_reg(cs, KVM_IOC_CSRID(LOONGARCH_CSR_PWCH),
+ &env->CSR_PWCH);
+
+ ret |= kvm_get_one_reg(cs, KVM_IOC_CSRID(LOONGARCH_CSR_STLBPS),
+ &env->CSR_STLBPS);
+
+ ret |= kvm_get_one_reg(cs, KVM_IOC_CSRID(LOONGARCH_CSR_RVACFG),
+ &env->CSR_RVACFG);
+
+ ret |= kvm_get_one_reg(cs, KVM_IOC_CSRID(LOONGARCH_CSR_CPUID),
+ &env->CSR_CPUID);
+
+ ret |= kvm_get_one_reg(cs, KVM_IOC_CSRID(LOONGARCH_CSR_PRCFG1),
+ &env->CSR_PRCFG1);
+
+ ret |= kvm_get_one_reg(cs, KVM_IOC_CSRID(LOONGARCH_CSR_PRCFG2),
+ &env->CSR_PRCFG2);
+
+ ret |= kvm_get_one_reg(cs, KVM_IOC_CSRID(LOONGARCH_CSR_PRCFG3),
+ &env->CSR_PRCFG3);
+
+ ret |= kvm_get_one_reg(cs, KVM_IOC_CSRID(LOONGARCH_CSR_SAVE(0)),
+ &env->CSR_SAVE[0]);
+
+ ret |= kvm_get_one_reg(cs, KVM_IOC_CSRID(LOONGARCH_CSR_SAVE(1)),
+ &env->CSR_SAVE[1]);
+
+ ret |= kvm_get_one_reg(cs, KVM_IOC_CSRID(LOONGARCH_CSR_SAVE(2)),
+ &env->CSR_SAVE[2]);
+
+ ret |= kvm_get_one_reg(cs, KVM_IOC_CSRID(LOONGARCH_CSR_SAVE(3)),
+ &env->CSR_SAVE[3]);
+
+ ret |= kvm_get_one_reg(cs, KVM_IOC_CSRID(LOONGARCH_CSR_SAVE(4)),
+ &env->CSR_SAVE[4]);
+
+ ret |= kvm_get_one_reg(cs, KVM_IOC_CSRID(LOONGARCH_CSR_SAVE(5)),
+ &env->CSR_SAVE[5]);
+
+ ret |= kvm_get_one_reg(cs, KVM_IOC_CSRID(LOONGARCH_CSR_SAVE(6)),
+ &env->CSR_SAVE[6]);
+
+ ret |= kvm_get_one_reg(cs, KVM_IOC_CSRID(LOONGARCH_CSR_SAVE(7)),
+ &env->CSR_SAVE[7]);
+
+ ret |= kvm_get_one_reg(cs, KVM_IOC_CSRID(LOONGARCH_CSR_TID),
+ &env->CSR_TID);
+
+ ret |= kvm_get_one_reg(cs, KVM_IOC_CSRID(LOONGARCH_CSR_CNTC),
+ &env->CSR_CNTC);
+
+ ret |= kvm_get_one_reg(cs, KVM_IOC_CSRID(LOONGARCH_CSR_TICLR),
+ &env->CSR_TICLR);
+
+ ret |= kvm_get_one_reg(cs, KVM_IOC_CSRID(LOONGARCH_CSR_LLBCTL),
+ &env->CSR_LLBCTL);
+
+ ret |= kvm_get_one_reg(cs, KVM_IOC_CSRID(LOONGARCH_CSR_IMPCTL1),
+ &env->CSR_IMPCTL1);
+
+ ret |= kvm_get_one_reg(cs, KVM_IOC_CSRID(LOONGARCH_CSR_IMPCTL2),
+ &env->CSR_IMPCTL2);
+
+ ret |= kvm_get_one_reg(cs, KVM_IOC_CSRID(LOONGARCH_CSR_TLBRENTRY),
+ &env->CSR_TLBRENTRY);
+
+ ret |= kvm_get_one_reg(cs, KVM_IOC_CSRID(LOONGARCH_CSR_TLBRBADV),
+ &env->CSR_TLBRBADV);
+
+ ret |= kvm_get_one_reg(cs, KVM_IOC_CSRID(LOONGARCH_CSR_TLBRERA),
+ &env->CSR_TLBRERA);
+
+ ret |= kvm_get_one_reg(cs, KVM_IOC_CSRID(LOONGARCH_CSR_TLBRSAVE),
+ &env->CSR_TLBRSAVE);
+
+ ret |= kvm_get_one_reg(cs, KVM_IOC_CSRID(LOONGARCH_CSR_TLBRELO0),
+ &env->CSR_TLBRELO0);
+
+ ret |= kvm_get_one_reg(cs, KVM_IOC_CSRID(LOONGARCH_CSR_TLBRELO1),
+ &env->CSR_TLBRELO1);
+
+ ret |= kvm_get_one_reg(cs, KVM_IOC_CSRID(LOONGARCH_CSR_TLBREHI),
+ &env->CSR_TLBREHI);
+
+ ret |= kvm_get_one_reg(cs, KVM_IOC_CSRID(LOONGARCH_CSR_TLBRPRMD),
+ &env->CSR_TLBRPRMD);
+
+ ret |= kvm_get_one_reg(cs, KVM_IOC_CSRID(LOONGARCH_CSR_DMW(0)),
+ &env->CSR_DMW[0]);
+
+ ret |= kvm_get_one_reg(cs, KVM_IOC_CSRID(LOONGARCH_CSR_DMW(1)),
+ &env->CSR_DMW[1]);
+
+ ret |= kvm_get_one_reg(cs, KVM_IOC_CSRID(LOONGARCH_CSR_DMW(2)),
+ &env->CSR_DMW[2]);
+
+ ret |= kvm_get_one_reg(cs, KVM_IOC_CSRID(LOONGARCH_CSR_DMW(3)),
+ &env->CSR_DMW[3]);
+
+ ret |= kvm_get_one_reg(cs, KVM_IOC_CSRID(LOONGARCH_CSR_TVAL),
+ &env->CSR_TVAL);
+
+ ret |= kvm_get_one_reg(cs, KVM_IOC_CSRID(LOONGARCH_CSR_TCFG),
+ &env->CSR_TCFG);
+
+ return ret;
+}
+
+static int kvm_loongarch_put_csr(CPUState *cs)
+{
+ int ret = 0;
+ LoongArchCPU *cpu = LOONGARCH_CPU(cs);
+ CPULoongArchState *env = &cpu->env;
+
+ ret |= kvm_set_one_reg(cs, KVM_IOC_CSRID(LOONGARCH_CSR_CRMD),
+ &env->CSR_CRMD);
+
+ ret |= kvm_set_one_reg(cs, KVM_IOC_CSRID(LOONGARCH_CSR_PRMD),
+ &env->CSR_PRMD);
+
+ ret |= kvm_set_one_reg(cs, KVM_IOC_CSRID(LOONGARCH_CSR_EUEN),
+ &env->CSR_EUEN);
+
+ ret |= kvm_set_one_reg(cs, KVM_IOC_CSRID(LOONGARCH_CSR_MISC),
+ &env->CSR_MISC);
+
+ ret |= kvm_set_one_reg(cs, KVM_IOC_CSRID(LOONGARCH_CSR_ECFG),
+ &env->CSR_ECFG);
+
+ ret |= kvm_set_one_reg(cs, KVM_IOC_CSRID(LOONGARCH_CSR_ESTAT),
+ &env->CSR_ESTAT);
+
+ ret |= kvm_set_one_reg(cs, KVM_IOC_CSRID(LOONGARCH_CSR_ERA),
+ &env->CSR_ERA);
+
+ ret |= kvm_set_one_reg(cs, KVM_IOC_CSRID(LOONGARCH_CSR_BADV),
+ &env->CSR_BADV);
+
+ ret |= kvm_set_one_reg(cs, KVM_IOC_CSRID(LOONGARCH_CSR_BADI),
+ &env->CSR_BADI);
+
+ ret |= kvm_set_one_reg(cs, KVM_IOC_CSRID(LOONGARCH_CSR_EENTRY),
+ &env->CSR_EENTRY);
+
+ ret |= kvm_set_one_reg(cs, KVM_IOC_CSRID(LOONGARCH_CSR_TLBIDX),
+ &env->CSR_TLBIDX);
+
+ ret |= kvm_set_one_reg(cs, KVM_IOC_CSRID(LOONGARCH_CSR_TLBEHI),
+ &env->CSR_TLBEHI);
+
+ ret |= kvm_set_one_reg(cs, KVM_IOC_CSRID(LOONGARCH_CSR_TLBELO0),
+ &env->CSR_TLBELO0);
+
+ ret |= kvm_set_one_reg(cs, KVM_IOC_CSRID(LOONGARCH_CSR_TLBELO1),
+ &env->CSR_TLBELO1);
+
+ ret |= kvm_set_one_reg(cs, KVM_IOC_CSRID(LOONGARCH_CSR_ASID),
+ &env->CSR_ASID);
+
+ ret |= kvm_set_one_reg(cs, KVM_IOC_CSRID(LOONGARCH_CSR_PGDL),
+ &env->CSR_PGDL);
+
+ ret |= kvm_set_one_reg(cs, KVM_IOC_CSRID(LOONGARCH_CSR_PGDH),
+ &env->CSR_PGDH);
+
+ ret |= kvm_set_one_reg(cs, KVM_IOC_CSRID(LOONGARCH_CSR_PGD),
+ &env->CSR_PGD);
+
+ ret |= kvm_set_one_reg(cs, KVM_IOC_CSRID(LOONGARCH_CSR_PWCL),
+ &env->CSR_PWCL);
+
+ ret |= kvm_set_one_reg(cs, KVM_IOC_CSRID(LOONGARCH_CSR_PWCH),
+ &env->CSR_PWCH);
+
+ ret |= kvm_set_one_reg(cs, KVM_IOC_CSRID(LOONGARCH_CSR_STLBPS),
+ &env->CSR_STLBPS);
+
+ ret |= kvm_set_one_reg(cs, KVM_IOC_CSRID(LOONGARCH_CSR_RVACFG),
+ &env->CSR_RVACFG);
+
+ ret |= kvm_set_one_reg(cs, KVM_IOC_CSRID(LOONGARCH_CSR_CPUID),
+ &env->CSR_CPUID);
+
+ ret |= kvm_set_one_reg(cs, KVM_IOC_CSRID(LOONGARCH_CSR_PRCFG1),
+ &env->CSR_PRCFG1);
+
+ ret |= kvm_set_one_reg(cs, KVM_IOC_CSRID(LOONGARCH_CSR_PRCFG2),
+ &env->CSR_PRCFG2);
+
+ ret |= kvm_set_one_reg(cs, KVM_IOC_CSRID(LOONGARCH_CSR_PRCFG3),
+ &env->CSR_PRCFG3);
+
+ ret |= kvm_set_one_reg(cs, KVM_IOC_CSRID(LOONGARCH_CSR_SAVE(0)),
+ &env->CSR_SAVE[0]);
+
+ ret |= kvm_set_one_reg(cs, KVM_IOC_CSRID(LOONGARCH_CSR_SAVE(1)),
+ &env->CSR_SAVE[1]);
+
+ ret |= kvm_set_one_reg(cs, KVM_IOC_CSRID(LOONGARCH_CSR_SAVE(2)),
+ &env->CSR_SAVE[2]);
+
+ ret |= kvm_set_one_reg(cs, KVM_IOC_CSRID(LOONGARCH_CSR_SAVE(3)),
+ &env->CSR_SAVE[3]);
+
+ ret |= kvm_set_one_reg(cs, KVM_IOC_CSRID(LOONGARCH_CSR_SAVE(4)),
+ &env->CSR_SAVE[4]);
+
+ ret |= kvm_set_one_reg(cs, KVM_IOC_CSRID(LOONGARCH_CSR_SAVE(5)),
+ &env->CSR_SAVE[5]);
+
+ ret |= kvm_set_one_reg(cs, KVM_IOC_CSRID(LOONGARCH_CSR_SAVE(6)),
+ &env->CSR_SAVE[6]);
+
+ ret |= kvm_set_one_reg(cs, KVM_IOC_CSRID(LOONGARCH_CSR_SAVE(7)),
+ &env->CSR_SAVE[7]);
+
+ ret |= kvm_set_one_reg(cs, KVM_IOC_CSRID(LOONGARCH_CSR_TID),
+ &env->CSR_TID);
+
+ ret |= kvm_set_one_reg(cs, KVM_IOC_CSRID(LOONGARCH_CSR_CNTC),
+ &env->CSR_CNTC);
+
+ ret |= kvm_set_one_reg(cs, KVM_IOC_CSRID(LOONGARCH_CSR_TICLR),
+ &env->CSR_TICLR);
+
+ ret |= kvm_set_one_reg(cs, KVM_IOC_CSRID(LOONGARCH_CSR_LLBCTL),
+ &env->CSR_LLBCTL);
+
+ ret |= kvm_set_one_reg(cs, KVM_IOC_CSRID(LOONGARCH_CSR_IMPCTL1),
+ &env->CSR_IMPCTL1);
+
+ ret |= kvm_set_one_reg(cs, KVM_IOC_CSRID(LOONGARCH_CSR_IMPCTL2),
+ &env->CSR_IMPCTL2);
+
+ ret |= kvm_set_one_reg(cs, KVM_IOC_CSRID(LOONGARCH_CSR_TLBRENTRY),
+ &env->CSR_TLBRENTRY);
+
+ ret |= kvm_set_one_reg(cs, KVM_IOC_CSRID(LOONGARCH_CSR_TLBRBADV),
+ &env->CSR_TLBRBADV);
+
+ ret |= kvm_set_one_reg(cs, KVM_IOC_CSRID(LOONGARCH_CSR_TLBRERA),
+ &env->CSR_TLBRERA);
+
+ ret |= kvm_set_one_reg(cs, KVM_IOC_CSRID(LOONGARCH_CSR_TLBRSAVE),
+ &env->CSR_TLBRSAVE);
+
+ ret |= kvm_set_one_reg(cs, KVM_IOC_CSRID(LOONGARCH_CSR_TLBRELO0),
+ &env->CSR_TLBRELO0);
+
+ ret |= kvm_set_one_reg(cs, KVM_IOC_CSRID(LOONGARCH_CSR_TLBRELO1),
+ &env->CSR_TLBRELO1);
+
+ ret |= kvm_set_one_reg(cs, KVM_IOC_CSRID(LOONGARCH_CSR_TLBREHI),
+ &env->CSR_TLBREHI);
+
+ ret |= kvm_set_one_reg(cs, KVM_IOC_CSRID(LOONGARCH_CSR_TLBRPRMD),
+ &env->CSR_TLBRPRMD);
+
+ ret |= kvm_set_one_reg(cs, KVM_IOC_CSRID(LOONGARCH_CSR_DMW(0)),
+ &env->CSR_DMW[0]);
+
+ ret |= kvm_set_one_reg(cs, KVM_IOC_CSRID(LOONGARCH_CSR_DMW(1)),
+ &env->CSR_DMW[1]);
+
+ ret |= kvm_set_one_reg(cs, KVM_IOC_CSRID(LOONGARCH_CSR_DMW(2)),
+ &env->CSR_DMW[2]);
+
+ ret |= kvm_set_one_reg(cs, KVM_IOC_CSRID(LOONGARCH_CSR_DMW(3)),
+ &env->CSR_DMW[3]);
+ /*
+ * timer cfg must be put at last since it is used to enable
+ * guest timer
+ */
+ ret |= kvm_set_one_reg(cs, KVM_IOC_CSRID(LOONGARCH_CSR_TVAL),
+ &env->CSR_TVAL);
+
+ ret |= kvm_set_one_reg(cs, KVM_IOC_CSRID(LOONGARCH_CSR_TCFG),
+ &env->CSR_TCFG);
+ return ret;
+}
+
+static int kvm_loongarch_get_regs_fp(CPUState *cs)
+{
+ int ret, i;
+ struct kvm_fpu fpu;
+
+ LoongArchCPU *cpu = LOONGARCH_CPU(cs);
+ CPULoongArchState *env = &cpu->env;
+
+ ret = kvm_vcpu_ioctl(cs, KVM_GET_FPU, &fpu);
+ if (ret < 0) {
+ trace_kvm_failed_get_fpu(strerror(errno));
+ return ret;
+ }
+
+ env->fcsr0 = fpu.fcsr;
+ for (i = 0; i < 32; i++) {
+ env->fpr[i].vreg.UD[0] = fpu.fpr[i].val64[0];
+ }
+ for (i = 0; i < 8; i++) {
+ env->cf[i] = fpu.fcc & 0xFF;
+ fpu.fcc = fpu.fcc >> 8;
+ }
+
+ return ret;
+}
+
+static int kvm_loongarch_put_regs_fp(CPUState *cs)
+{
+ int ret, i;
+ struct kvm_fpu fpu;
+
+ LoongArchCPU *cpu = LOONGARCH_CPU(cs);
+ CPULoongArchState *env = &cpu->env;
+
+ fpu.fcsr = env->fcsr0;
+ fpu.fcc = 0;
+ for (i = 0; i < 32; i++) {
+ fpu.fpr[i].val64[0] = env->fpr[i].vreg.UD[0];
+ }
+
+ for (i = 0; i < 8; i++) {
+ fpu.fcc |= env->cf[i] << (8 * i);
+ }
+
+ ret = kvm_vcpu_ioctl(cs, KVM_SET_FPU, &fpu);
+ if (ret < 0) {
+ trace_kvm_failed_put_fpu(strerror(errno));
+ }
+
+ return ret;
+}
+
+void kvm_arch_reset_vcpu(CPULoongArchState *env)
+{
+ env->mp_state = KVM_MP_STATE_RUNNABLE;
+}
+
+static int kvm_loongarch_get_mpstate(CPUState *cs)
+{
+ int ret = 0;
+ struct kvm_mp_state mp_state;
+ LoongArchCPU *cpu = LOONGARCH_CPU(cs);
+ CPULoongArchState *env = &cpu->env;
+
+ if (cap_has_mp_state) {
+ ret = kvm_vcpu_ioctl(cs, KVM_GET_MP_STATE, &mp_state);
+ if (ret) {
+ trace_kvm_failed_get_mpstate(strerror(errno));
+ return ret;
+ }
+ env->mp_state = mp_state.mp_state;
+ }
+
+ return ret;
+}
+
+static int kvm_loongarch_put_mpstate(CPUState *cs)
+{
+ int ret = 0;
+
+ LoongArchCPU *cpu = LOONGARCH_CPU(cs);
+ CPULoongArchState *env = &cpu->env;
+
+ struct kvm_mp_state mp_state = {
+ .mp_state = env->mp_state
+ };
+
+ if (cap_has_mp_state) {
+ ret = kvm_vcpu_ioctl(cs, KVM_SET_MP_STATE, &mp_state);
+ if (ret) {
+ trace_kvm_failed_put_mpstate(strerror(errno));
+ }
+ }
+
+ return ret;
+}
+
+static int kvm_loongarch_get_cpucfg(CPUState *cs)
+{
+ int i, ret = 0;
+ uint64_t val;
+ LoongArchCPU *cpu = LOONGARCH_CPU(cs);
+ CPULoongArchState *env = &cpu->env;
+
+ for (i = 0; i < 21; i++) {
+ ret = kvm_get_one_reg(cs, KVM_IOC_CPUCFG(i), &val);
+ if (ret < 0) {
+ trace_kvm_failed_get_cpucfg(strerror(errno));
+ }
+ env->cpucfg[i] = (uint32_t)val;
+ }
+ return ret;
+}
+
+static int kvm_loongarch_put_cpucfg(CPUState *cs)
+{
+ int i, ret = 0;
+ LoongArchCPU *cpu = LOONGARCH_CPU(cs);
+ CPULoongArchState *env = &cpu->env;
+ uint64_t val;
+
+ for (i = 0; i < 21; i++) {
+ val = env->cpucfg[i];
+ /* LSX and LASX and LBT are not supported in kvm now */
+ if (i == 2) {
+ val &= ~(BIT(R_CPUCFG2_LSX_SHIFT) | BIT(R_CPUCFG2_LASX_SHIFT));
+ val &= ~(BIT(R_CPUCFG2_LBT_X86_SHIFT) |
+ BIT(R_CPUCFG2_LBT_ARM_SHIFT) |
+ BIT(R_CPUCFG2_LBT_MIPS_SHIFT));
+ }
+ ret = kvm_set_one_reg(cs, KVM_IOC_CPUCFG(i), &val);
+ if (ret < 0) {
+ trace_kvm_failed_put_cpucfg(strerror(errno));
+ }
+ }
+ return ret;
+}
+
int kvm_arch_get_registers(CPUState *cs)
{
- return 0;
+ int ret;
+
+ ret = kvm_loongarch_get_regs_core(cs);
+ if (ret) {
+ return ret;
+ }
+
+ ret = kvm_loongarch_get_csr(cs);
+ if (ret) {
+ return ret;
+ }
+
+ ret = kvm_loongarch_get_regs_fp(cs);
+ if (ret) {
+ return ret;
+ }
+
+ ret = kvm_loongarch_get_mpstate(cs);
+ if (ret) {
+ return ret;
+ }
+
+ ret = kvm_loongarch_get_cpucfg(cs);
+ return ret;
}
+
int kvm_arch_put_registers(CPUState *cs, int level)
{
- return 0;
+ int ret;
+
+ ret = kvm_loongarch_put_regs_core(cs);
+ if (ret) {
+ return ret;
+ }
+
+ ret = kvm_loongarch_put_csr(cs);
+ if (ret) {
+ return ret;
+ }
+
+ ret = kvm_loongarch_put_regs_fp(cs);
+ if (ret) {
+ return ret;
+ }
+
+ ret = kvm_loongarch_put_mpstate(cs);
+ if (ret) {
+ return ret;
+ }
+
+ ret = kvm_loongarch_put_cpucfg(cs);
+ return ret;
}
int kvm_arch_init_vcpu(CPUState *cs)
diff --git a/target/loongarch/trace-events b/target/loongarch/trace-events
new file mode 100644
index 0000000000..6827ab566a
--- /dev/null
+++ b/target/loongarch/trace-events
@@ -0,0 +1,11 @@
+# See docs/devel/tracing.rst for syntax documentation.
+
+#kvm.c
+kvm_failed_get_regs_core(const char *msg) "Failed to get core regs from KVM: %s"
+kvm_failed_put_regs_core(const char *msg) "Failed to put core regs into KVM: %s"
+kvm_failed_get_fpu(const char *msg) "Failed to get fpu from KVM: %s"
+kvm_failed_put_fpu(const char *msg) "Failed to put fpu into KVM: %s"
+kvm_failed_get_mpstate(const char *msg) "Failed to get mp_state from KVM: %s"
+kvm_failed_put_mpstate(const char *msg) "Failed to put mp_state into KVM: %s"
+kvm_failed_get_cpucfg(const char *msg) "Failed to get cpucfg from KVM: %s"
+kvm_failed_put_cpucfg(const char *msg) "Failed to put cpucfg into KVM: %s"
diff --git a/target/loongarch/trace.h b/target/loongarch/trace.h
new file mode 100644
index 0000000000..c2ecb78f08
--- /dev/null
+++ b/target/loongarch/trace.h
@@ -0,0 +1 @@
+#include "trace/trace-target_loongarch.h"
--
2.39.1
^ permalink raw reply related [flat|nested] 19+ messages in thread* [PATCH v4 5/9] target/loongarch: Implement kvm_arch_init function
2024-01-05 7:57 [PATCH v4 0/9] Add loongarch kvm accel support Tianrui Zhao
` (3 preceding siblings ...)
2024-01-05 7:57 ` [PATCH v4 4/9] target/loongarch: Implement kvm get/set registers Tianrui Zhao
@ 2024-01-05 7:58 ` Tianrui Zhao
2024-01-05 7:58 ` [PATCH v4 6/9] target/loongarch: Implement kvm_arch_init_vcpu Tianrui Zhao
` (4 subsequent siblings)
9 siblings, 0 replies; 19+ messages in thread
From: Tianrui Zhao @ 2024-01-05 7:58 UTC (permalink / raw)
To: qemu-devel
Cc: gaosong, maobibo, zhaotianrui, mst, cohuck, pbonzini,
marcandre.lureau, berrange, thuth, philmd, richard.henderson,
peter.maydell, yangxiaojuan, xianglai li
Implement the kvm_arch_init of loongarch, in the function, the
KVM_CAP_MP_STATE cap is checked by kvm ioctl.
Signed-off-by: Tianrui Zhao <zhaotianrui@loongson.cn>
Signed-off-by: xianglai li <lixianglai@loongson.cn>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Song Gao <gaosong@loongson.cn>
---
target/loongarch/kvm/kvm.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/target/loongarch/kvm/kvm.c b/target/loongarch/kvm/kvm.c
index e7c9ef830c..29944b9ef8 100644
--- a/target/loongarch/kvm/kvm.c
+++ b/target/loongarch/kvm/kvm.c
@@ -665,6 +665,7 @@ int kvm_arch_get_default_type(MachineState *ms)
int kvm_arch_init(MachineState *ms, KVMState *s)
{
+ cap_has_mp_state = kvm_check_extension(s, KVM_CAP_MP_STATE);
return 0;
}
--
2.39.1
^ permalink raw reply related [flat|nested] 19+ messages in thread* [PATCH v4 6/9] target/loongarch: Implement kvm_arch_init_vcpu
2024-01-05 7:57 [PATCH v4 0/9] Add loongarch kvm accel support Tianrui Zhao
` (4 preceding siblings ...)
2024-01-05 7:58 ` [PATCH v4 5/9] target/loongarch: Implement kvm_arch_init function Tianrui Zhao
@ 2024-01-05 7:58 ` Tianrui Zhao
2024-01-05 7:58 ` [PATCH v4 7/9] target/loongarch: Implement kvm_arch_handle_exit Tianrui Zhao
` (3 subsequent siblings)
9 siblings, 0 replies; 19+ messages in thread
From: Tianrui Zhao @ 2024-01-05 7:58 UTC (permalink / raw)
To: qemu-devel
Cc: gaosong, maobibo, zhaotianrui, mst, cohuck, pbonzini,
marcandre.lureau, berrange, thuth, philmd, richard.henderson,
peter.maydell, yangxiaojuan, xianglai li
Implement kvm_arch_init_vcpu interface for loongarch,
in this function, we register VM change state handler.
And when VM state changes to running, the counter value
should be put into kvm to keep consistent with kvm,
and when state change to stop, counter value should be
refreshed from kvm.
Signed-off-by: Tianrui Zhao <zhaotianrui@loongson.cn>
Signed-off-by: xianglai li <lixianglai@loongson.cn>
Reviewed-by: Song Gao <gaosong@loongson.cn>
---
target/loongarch/cpu.h | 2 ++
target/loongarch/kvm/kvm.c | 23 +++++++++++++++++++++++
target/loongarch/trace-events | 2 ++
3 files changed, 27 insertions(+)
diff --git a/target/loongarch/cpu.h b/target/loongarch/cpu.h
index f4a89bd626..8ebd6fa1a7 100644
--- a/target/loongarch/cpu.h
+++ b/target/loongarch/cpu.h
@@ -381,6 +381,8 @@ struct ArchCPU {
/* 'compatible' string for this CPU for Linux device trees */
const char *dtb_compatible;
+ /* used by KVM_REG_LOONGARCH_COUNTER ioctl to access guest time counters */
+ uint64_t kvm_state_counter;
};
/**
diff --git a/target/loongarch/kvm/kvm.c b/target/loongarch/kvm/kvm.c
index 29944b9ef8..85e7aeb083 100644
--- a/target/loongarch/kvm/kvm.c
+++ b/target/loongarch/kvm/kvm.c
@@ -617,8 +617,31 @@ int kvm_arch_put_registers(CPUState *cs, int level)
return ret;
}
+static void kvm_loongarch_vm_stage_change(void *opaque, bool running,
+ RunState state)
+{
+ int ret;
+ CPUState *cs = opaque;
+ LoongArchCPU *cpu = LOONGARCH_CPU(cs);
+
+ if (running) {
+ ret = kvm_set_one_reg(cs, KVM_REG_LOONGARCH_COUNTER,
+ &cpu->kvm_state_counter);
+ if (ret < 0) {
+ trace_kvm_failed_put_counter(strerror(errno));
+ }
+ } else {
+ ret = kvm_get_one_reg(cs, KVM_REG_LOONGARCH_COUNTER,
+ &cpu->kvm_state_counter);
+ if (ret < 0) {
+ trace_kvm_failed_get_counter(strerror(errno));
+ }
+ }
+}
+
int kvm_arch_init_vcpu(CPUState *cs)
{
+ qemu_add_vm_change_state_handler(kvm_loongarch_vm_stage_change, cs);
return 0;
}
diff --git a/target/loongarch/trace-events b/target/loongarch/trace-events
index 6827ab566a..937c3c7c0c 100644
--- a/target/loongarch/trace-events
+++ b/target/loongarch/trace-events
@@ -7,5 +7,7 @@ kvm_failed_get_fpu(const char *msg) "Failed to get fpu from KVM: %s"
kvm_failed_put_fpu(const char *msg) "Failed to put fpu into KVM: %s"
kvm_failed_get_mpstate(const char *msg) "Failed to get mp_state from KVM: %s"
kvm_failed_put_mpstate(const char *msg) "Failed to put mp_state into KVM: %s"
+kvm_failed_get_counter(const char *msg) "Failed to get counter from KVM: %s"
+kvm_failed_put_counter(const char *msg) "Failed to put counter into KVM: %s"
kvm_failed_get_cpucfg(const char *msg) "Failed to get cpucfg from KVM: %s"
kvm_failed_put_cpucfg(const char *msg) "Failed to put cpucfg into KVM: %s"
--
2.39.1
^ permalink raw reply related [flat|nested] 19+ messages in thread* [PATCH v4 7/9] target/loongarch: Implement kvm_arch_handle_exit
2024-01-05 7:57 [PATCH v4 0/9] Add loongarch kvm accel support Tianrui Zhao
` (5 preceding siblings ...)
2024-01-05 7:58 ` [PATCH v4 6/9] target/loongarch: Implement kvm_arch_init_vcpu Tianrui Zhao
@ 2024-01-05 7:58 ` Tianrui Zhao
2024-01-05 7:58 ` [PATCH v4 8/9] target/loongarch: Implement set vcpu intr for kvm Tianrui Zhao
` (2 subsequent siblings)
9 siblings, 0 replies; 19+ messages in thread
From: Tianrui Zhao @ 2024-01-05 7:58 UTC (permalink / raw)
To: qemu-devel
Cc: gaosong, maobibo, zhaotianrui, mst, cohuck, pbonzini,
marcandre.lureau, berrange, thuth, philmd, richard.henderson,
peter.maydell, yangxiaojuan, xianglai li
Implement kvm_arch_handle_exit for loongarch. In this
function, the KVM_EXIT_LOONGARCH_IOCSR is handled,
we read or write the iocsr address space by the addr,
length and is_write argument in kvm_run.
Signed-off-by: Tianrui Zhao <zhaotianrui@loongson.cn>
Signed-off-by: xianglai li <lixianglai@loongson.cn>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Song Gao <gaosong@loongson.cn>
---
target/loongarch/kvm/kvm.c | 24 +++++++++++++++++++++++-
target/loongarch/trace-events | 1 +
2 files changed, 24 insertions(+), 1 deletion(-)
diff --git a/target/loongarch/kvm/kvm.c b/target/loongarch/kvm/kvm.c
index 85e7aeb083..d2dab3fef4 100644
--- a/target/loongarch/kvm/kvm.c
+++ b/target/loongarch/kvm/kvm.c
@@ -723,7 +723,29 @@ bool kvm_arch_cpu_check_are_resettable(void)
int kvm_arch_handle_exit(CPUState *cs, struct kvm_run *run)
{
- return 0;
+ int ret = 0;
+ LoongArchCPU *cpu = LOONGARCH_CPU(cs);
+ CPULoongArchState *env = &cpu->env;
+ MemTxAttrs attrs = {};
+
+ attrs.requester_id = env_cpu(env)->cpu_index;
+
+ trace_kvm_arch_handle_exit(run->exit_reason);
+ switch (run->exit_reason) {
+ case KVM_EXIT_LOONGARCH_IOCSR:
+ address_space_rw(&env->address_space_iocsr,
+ run->iocsr_io.phys_addr,
+ attrs,
+ run->iocsr_io.data,
+ run->iocsr_io.len,
+ run->iocsr_io.is_write);
+ break;
+ default:
+ ret = -1;
+ warn_report("KVM: unknown exit reason %d", run->exit_reason);
+ break;
+ }
+ return ret;
}
void kvm_arch_accel_class_init(ObjectClass *oc)
diff --git a/target/loongarch/trace-events b/target/loongarch/trace-events
index 937c3c7c0c..021839880e 100644
--- a/target/loongarch/trace-events
+++ b/target/loongarch/trace-events
@@ -11,3 +11,4 @@ kvm_failed_get_counter(const char *msg) "Failed to get counter from KVM: %s"
kvm_failed_put_counter(const char *msg) "Failed to put counter into KVM: %s"
kvm_failed_get_cpucfg(const char *msg) "Failed to get cpucfg from KVM: %s"
kvm_failed_put_cpucfg(const char *msg) "Failed to put cpucfg into KVM: %s"
+kvm_arch_handle_exit(int num) "kvm arch handle exit, the reason number: %d"
--
2.39.1
^ permalink raw reply related [flat|nested] 19+ messages in thread* [PATCH v4 8/9] target/loongarch: Implement set vcpu intr for kvm
2024-01-05 7:57 [PATCH v4 0/9] Add loongarch kvm accel support Tianrui Zhao
` (6 preceding siblings ...)
2024-01-05 7:58 ` [PATCH v4 7/9] target/loongarch: Implement kvm_arch_handle_exit Tianrui Zhao
@ 2024-01-05 7:58 ` Tianrui Zhao
2024-01-10 9:20 ` Philippe Mathieu-Daudé
` (2 more replies)
2024-01-05 7:58 ` [PATCH v4 9/9] target/loongarch: Add loongarch kvm into meson build Tianrui Zhao
2024-01-10 2:46 ` [PATCH v4 0/9] Add loongarch kvm accel support gaosong
9 siblings, 3 replies; 19+ messages in thread
From: Tianrui Zhao @ 2024-01-05 7:58 UTC (permalink / raw)
To: qemu-devel
Cc: gaosong, maobibo, zhaotianrui, mst, cohuck, pbonzini,
marcandre.lureau, berrange, thuth, philmd, richard.henderson,
peter.maydell, yangxiaojuan, xianglai li
Implement loongarch kvm set vcpu interrupt interface,
when a irq is set in vcpu, we use the KVM_INTERRUPT
ioctl to set intr into kvm.
Signed-off-by: Tianrui Zhao <zhaotianrui@loongson.cn>
Signed-off-by: xianglai li <lixianglai@loongson.cn>
Reviewed-by: Song Gao <gaosong@loongson.cn>
---
target/loongarch/cpu.c | 34 +++++++++++++++++++++-------
target/loongarch/kvm/kvm.c | 15 ++++++++++++
target/loongarch/kvm/kvm_loongarch.h | 16 +++++++++++++
target/loongarch/trace-events | 1 +
4 files changed, 58 insertions(+), 8 deletions(-)
create mode 100644 target/loongarch/kvm/kvm_loongarch.h
diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c
index 6614a094c8..dfbbe0ace1 100644
--- a/target/loongarch/cpu.c
+++ b/target/loongarch/cpu.c
@@ -11,7 +11,6 @@
#include "qapi/error.h"
#include "qemu/module.h"
#include "sysemu/qtest.h"
-#include "exec/cpu_ldst.h"
#include "exec/exec-all.h"
#include "cpu.h"
#include "internals.h"
@@ -20,8 +19,16 @@
#ifndef CONFIG_USER_ONLY
#include "sysemu/reset.h"
#endif
-#include "tcg/tcg.h"
#include "vec.h"
+#include "sysemu/kvm.h"
+#include "kvm/kvm_loongarch.h"
+#ifdef CONFIG_KVM
+#include <linux/kvm.h>
+#endif
+#ifdef CONFIG_TCG
+#include "exec/cpu_ldst.h"
+#include "tcg/tcg.h"
+#endif
const char * const regnames[32] = {
"r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
@@ -110,12 +117,15 @@ void loongarch_cpu_set_irq(void *opaque, int irq, int level)
return;
}
- env->CSR_ESTAT = deposit64(env->CSR_ESTAT, irq, 1, level != 0);
-
- if (FIELD_EX64(env->CSR_ESTAT, CSR_ESTAT, IS)) {
- cpu_interrupt(cs, CPU_INTERRUPT_HARD);
+ if (kvm_enabled()) {
+ kvm_loongarch_set_interrupt(cpu, irq, level);
} else {
- cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD);
+ env->CSR_ESTAT = deposit64(env->CSR_ESTAT, irq, 1, level != 0);
+ if (FIELD_EX64(env->CSR_ESTAT, CSR_ESTAT, IS)) {
+ cpu_interrupt(cs, CPU_INTERRUPT_HARD);
+ } else {
+ cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD);
+ }
}
}
@@ -140,7 +150,10 @@ static inline bool cpu_loongarch_hw_interrupts_pending(CPULoongArchState *env)
return (pending & status) != 0;
}
+#endif
+#ifdef CONFIG_TCG
+#ifndef CONFIG_USER_ONLY
static void loongarch_cpu_do_interrupt(CPUState *cs)
{
LoongArchCPU *cpu = LOONGARCH_CPU(cs);
@@ -322,7 +335,6 @@ static bool loongarch_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
}
#endif
-#ifdef CONFIG_TCG
static void loongarch_cpu_synchronize_from_tb(CPUState *cs,
const TranslationBlock *tb)
{
@@ -560,7 +572,9 @@ static void loongarch_cpu_reset_hold(Object *obj)
}
#endif
+#ifdef CONFIG_TCG
restore_fp_status(env);
+#endif
cs->exception_index = -1;
}
@@ -703,8 +717,10 @@ static void loongarch_cpu_init(Object *obj)
CPULoongArchState *env = &cpu->env;
qdev_init_gpio_in(DEVICE(cpu), loongarch_cpu_set_irq, N_IRQS);
+#ifdef CONFIG_TCG
timer_init_ns(&cpu->timer, QEMU_CLOCK_VIRTUAL,
&loongarch_constant_timer_cb, cpu);
+#endif
memory_region_init_io(&env->system_iocsr, OBJECT(cpu), NULL,
env, "iocsr", UINT64_MAX);
address_space_init(&env->address_space_iocsr, &env->system_iocsr, "IOCSR");
@@ -804,7 +820,9 @@ static struct TCGCPUOps loongarch_tcg_ops = {
#include "hw/core/sysemu-cpu-ops.h"
static const struct SysemuCPUOps loongarch_sysemu_ops = {
+#ifdef CONFIG_TCG
.get_phys_page_debug = loongarch_cpu_get_phys_page_debug,
+#endif
};
static int64_t loongarch_cpu_get_arch_id(CPUState *cs)
diff --git a/target/loongarch/kvm/kvm.c b/target/loongarch/kvm/kvm.c
index d2dab3fef4..bd33ec2114 100644
--- a/target/loongarch/kvm/kvm.c
+++ b/target/loongarch/kvm/kvm.c
@@ -748,6 +748,21 @@ int kvm_arch_handle_exit(CPUState *cs, struct kvm_run *run)
return ret;
}
+int kvm_loongarch_set_interrupt(LoongArchCPU *cpu, int irq, int level)
+{
+ struct kvm_interrupt intr;
+ CPUState *cs = CPU(cpu);
+
+ if (level) {
+ intr.irq = irq;
+ } else {
+ intr.irq = -irq;
+ }
+
+ trace_kvm_set_intr(irq, level);
+ return kvm_vcpu_ioctl(cs, KVM_INTERRUPT, &intr);
+}
+
void kvm_arch_accel_class_init(ObjectClass *oc)
{
}
diff --git a/target/loongarch/kvm/kvm_loongarch.h b/target/loongarch/kvm/kvm_loongarch.h
new file mode 100644
index 0000000000..d945b6bb82
--- /dev/null
+++ b/target/loongarch/kvm/kvm_loongarch.h
@@ -0,0 +1,16 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/*
+ * QEMU LoongArch kvm interface
+ *
+ * Copyright (c) 2023 Loongson Technology Corporation Limited
+ */
+
+#include "cpu.h"
+
+#ifndef QEMU_KVM_LOONGARCH_H
+#define QEMU_KVM_LOONGARCH_H
+
+int kvm_loongarch_set_interrupt(LoongArchCPU *cpu, int irq, int level);
+void kvm_arch_reset_vcpu(CPULoongArchState *env);
+
+#endif
diff --git a/target/loongarch/trace-events b/target/loongarch/trace-events
index 021839880e..dea11edc0f 100644
--- a/target/loongarch/trace-events
+++ b/target/loongarch/trace-events
@@ -12,3 +12,4 @@ kvm_failed_put_counter(const char *msg) "Failed to put counter into KVM: %s"
kvm_failed_get_cpucfg(const char *msg) "Failed to get cpucfg from KVM: %s"
kvm_failed_put_cpucfg(const char *msg) "Failed to put cpucfg into KVM: %s"
kvm_arch_handle_exit(int num) "kvm arch handle exit, the reason number: %d"
+kvm_set_intr(int irq, int level) "kvm set interrupt, irq num: %d, level: %d"
--
2.39.1
^ permalink raw reply related [flat|nested] 19+ messages in thread* Re: [PATCH v4 8/9] target/loongarch: Implement set vcpu intr for kvm
2024-01-05 7:58 ` [PATCH v4 8/9] target/loongarch: Implement set vcpu intr for kvm Tianrui Zhao
@ 2024-01-10 9:20 ` Philippe Mathieu-Daudé
2024-01-10 9:41 ` [PATCH v4 8/9a] target/loongarch: Restrict TCG-specific code Philippe Mathieu-Daudé
2024-01-10 9:41 ` [PATCH v4 8/9b] target/loongarch: Implement set vcpu intr for kvm Philippe Mathieu-Daudé
2 siblings, 0 replies; 19+ messages in thread
From: Philippe Mathieu-Daudé @ 2024-01-10 9:20 UTC (permalink / raw)
To: Tianrui Zhao, qemu-devel
Cc: gaosong, maobibo, mst, cohuck, pbonzini, marcandre.lureau,
berrange, thuth, richard.henderson, peter.maydell, yangxiaojuan,
xianglai li
Hi Tianrui,
On 5/1/24 08:58, Tianrui Zhao wrote:
> Implement loongarch kvm set vcpu interrupt interface,
> when a irq is set in vcpu, we use the KVM_INTERRUPT
> ioctl to set intr into kvm.
>
> Signed-off-by: Tianrui Zhao <zhaotianrui@loongson.cn>
> Signed-off-by: xianglai li <lixianglai@loongson.cn>
> Reviewed-by: Song Gao <gaosong@loongson.cn>
> ---
> target/loongarch/cpu.c | 34 +++++++++++++++++++++-------
> target/loongarch/kvm/kvm.c | 15 ++++++++++++
> target/loongarch/kvm/kvm_loongarch.h | 16 +++++++++++++
> target/loongarch/trace-events | 1 +
> 4 files changed, 58 insertions(+), 8 deletions(-)
> create mode 100644 target/loongarch/kvm/kvm_loongarch.h
>
> diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c
> index 6614a094c8..dfbbe0ace1 100644
> --- a/target/loongarch/cpu.c
> +++ b/target/loongarch/cpu.c
> @@ -11,7 +11,6 @@
> #include "qapi/error.h"
> #include "qemu/module.h"
> #include "sysemu/qtest.h"
> -#include "exec/cpu_ldst.h"
> #include "exec/exec-all.h"
> #include "cpu.h"
> #include "internals.h"
> @@ -20,8 +19,16 @@
> #ifndef CONFIG_USER_ONLY
> #include "sysemu/reset.h"
> #endif
> -#include "tcg/tcg.h"
> #include "vec.h"
> +#include "sysemu/kvm.h"
> +#include "kvm/kvm_loongarch.h"
Shouldn't this header ^ ...
> +#ifdef CONFIG_KVM
... goes here?
> +#include <linux/kvm.h>
> +#endif
> +#ifdef CONFIG_TCG
> +#include "exec/cpu_ldst.h"
> +#include "tcg/tcg.h"
> +#endif
^ permalink raw reply [flat|nested] 19+ messages in thread
* [PATCH v4 8/9a] target/loongarch: Restrict TCG-specific code
2024-01-05 7:58 ` [PATCH v4 8/9] target/loongarch: Implement set vcpu intr for kvm Tianrui Zhao
2024-01-10 9:20 ` Philippe Mathieu-Daudé
@ 2024-01-10 9:41 ` Philippe Mathieu-Daudé
2024-01-10 9:41 ` [PATCH v4 8/9b] target/loongarch: Implement set vcpu intr for kvm Philippe Mathieu-Daudé
2 siblings, 0 replies; 19+ messages in thread
From: Philippe Mathieu-Daudé @ 2024-01-10 9:41 UTC (permalink / raw)
To: qemu-devel
Cc: Song Gao, Tianrui Zhao, xianglai li, Philippe Mathieu-Daudé
From: Tianrui Zhao <zhaotianrui@loongson.cn>
In preparation of supporting KVM in the next commit.
Signed-off-by: Tianrui Zhao <zhaotianrui@loongson.cn>
Signed-off-by: xianglai li <lixianglai@loongson.cn>
Reviewed-by: Song Gao <gaosong@loongson.cn>
Message-ID: <20240105075804.1228596-9-zhaotianrui@loongson.cn>
[PMD: Split from bigger patch, part 1]
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
target/loongarch/cpu.c | 30 +++++++++++++++++++++---------
1 file changed, 21 insertions(+), 9 deletions(-)
diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c
index 6614a094c8..d9f8661cfd 100644
--- a/target/loongarch/cpu.c
+++ b/target/loongarch/cpu.c
@@ -11,7 +11,7 @@
#include "qapi/error.h"
#include "qemu/module.h"
#include "sysemu/qtest.h"
-#include "exec/cpu_ldst.h"
+#include "sysemu/tcg.h"
#include "exec/exec-all.h"
#include "cpu.h"
#include "internals.h"
@@ -20,8 +20,11 @@
#ifndef CONFIG_USER_ONLY
#include "sysemu/reset.h"
#endif
-#include "tcg/tcg.h"
#include "vec.h"
+#ifdef CONFIG_TCG
+#include "exec/cpu_ldst.h"
+#include "tcg/tcg.h"
+#endif
const char * const regnames[32] = {
"r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
@@ -110,12 +113,13 @@ void loongarch_cpu_set_irq(void *opaque, int irq, int level)
return;
}
- env->CSR_ESTAT = deposit64(env->CSR_ESTAT, irq, 1, level != 0);
-
- if (FIELD_EX64(env->CSR_ESTAT, CSR_ESTAT, IS)) {
- cpu_interrupt(cs, CPU_INTERRUPT_HARD);
- } else {
- cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD);
+ if (tcg_enabled()) {
+ env->CSR_ESTAT = deposit64(env->CSR_ESTAT, irq, 1, level != 0);
+ if (FIELD_EX64(env->CSR_ESTAT, CSR_ESTAT, IS)) {
+ cpu_interrupt(cs, CPU_INTERRUPT_HARD);
+ } else {
+ cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD);
+ }
}
}
@@ -140,7 +144,10 @@ static inline bool cpu_loongarch_hw_interrupts_pending(CPULoongArchState *env)
return (pending & status) != 0;
}
+#endif
+#ifdef CONFIG_TCG
+#ifndef CONFIG_USER_ONLY
static void loongarch_cpu_do_interrupt(CPUState *cs)
{
LoongArchCPU *cpu = LOONGARCH_CPU(cs);
@@ -322,7 +329,6 @@ static bool loongarch_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
}
#endif
-#ifdef CONFIG_TCG
static void loongarch_cpu_synchronize_from_tb(CPUState *cs,
const TranslationBlock *tb)
{
@@ -560,7 +566,9 @@ static void loongarch_cpu_reset_hold(Object *obj)
}
#endif
+#ifdef CONFIG_TCG
restore_fp_status(env);
+#endif
cs->exception_index = -1;
}
@@ -703,8 +711,10 @@ static void loongarch_cpu_init(Object *obj)
CPULoongArchState *env = &cpu->env;
qdev_init_gpio_in(DEVICE(cpu), loongarch_cpu_set_irq, N_IRQS);
+#ifdef CONFIG_TCG
timer_init_ns(&cpu->timer, QEMU_CLOCK_VIRTUAL,
&loongarch_constant_timer_cb, cpu);
+#endif
memory_region_init_io(&env->system_iocsr, OBJECT(cpu), NULL,
env, "iocsr", UINT64_MAX);
address_space_init(&env->address_space_iocsr, &env->system_iocsr, "IOCSR");
@@ -804,7 +814,9 @@ static struct TCGCPUOps loongarch_tcg_ops = {
#include "hw/core/sysemu-cpu-ops.h"
static const struct SysemuCPUOps loongarch_sysemu_ops = {
+#ifdef CONFIG_TCG
.get_phys_page_debug = loongarch_cpu_get_phys_page_debug,
+#endif
};
static int64_t loongarch_cpu_get_arch_id(CPUState *cs)
--
2.41.0
^ permalink raw reply related [flat|nested] 19+ messages in thread* [PATCH v4 8/9b] target/loongarch: Implement set vcpu intr for kvm
2024-01-05 7:58 ` [PATCH v4 8/9] target/loongarch: Implement set vcpu intr for kvm Tianrui Zhao
2024-01-10 9:20 ` Philippe Mathieu-Daudé
2024-01-10 9:41 ` [PATCH v4 8/9a] target/loongarch: Restrict TCG-specific code Philippe Mathieu-Daudé
@ 2024-01-10 9:41 ` Philippe Mathieu-Daudé
2024-01-11 2:29 ` gaosong
2 siblings, 1 reply; 19+ messages in thread
From: Philippe Mathieu-Daudé @ 2024-01-10 9:41 UTC (permalink / raw)
To: qemu-devel
Cc: Song Gao, Tianrui Zhao, xianglai li, Philippe Mathieu-Daudé
From: Tianrui Zhao <zhaotianrui@loongson.cn>
Implement loongarch kvm set vcpu interrupt interface,
when a irq is set in vcpu, we use the KVM_INTERRUPT
ioctl to set intr into kvm.
Signed-off-by: Tianrui Zhao <zhaotianrui@loongson.cn>
Signed-off-by: xianglai li <lixianglai@loongson.cn>
Reviewed-by: Song Gao <gaosong@loongson.cn>
Message-ID: <20240105075804.1228596-9-zhaotianrui@loongson.cn>
[PMD: Split from bigger patch, part 2]
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
target/loongarch/kvm/kvm_loongarch.h | 16 ++++++++++++++++
target/loongarch/cpu.c | 9 ++++++++-
target/loongarch/kvm/kvm.c | 15 +++++++++++++++
target/loongarch/trace-events | 1 +
4 files changed, 40 insertions(+), 1 deletion(-)
create mode 100644 target/loongarch/kvm/kvm_loongarch.h
diff --git a/target/loongarch/kvm/kvm_loongarch.h b/target/loongarch/kvm/kvm_loongarch.h
new file mode 100644
index 0000000000..d945b6bb82
--- /dev/null
+++ b/target/loongarch/kvm/kvm_loongarch.h
@@ -0,0 +1,16 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/*
+ * QEMU LoongArch kvm interface
+ *
+ * Copyright (c) 2023 Loongson Technology Corporation Limited
+ */
+
+#include "cpu.h"
+
+#ifndef QEMU_KVM_LOONGARCH_H
+#define QEMU_KVM_LOONGARCH_H
+
+int kvm_loongarch_set_interrupt(LoongArchCPU *cpu, int irq, int level);
+void kvm_arch_reset_vcpu(CPULoongArchState *env);
+
+#endif
diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c
index d9f8661cfd..d3a8a2f521 100644
--- a/target/loongarch/cpu.c
+++ b/target/loongarch/cpu.c
@@ -12,6 +12,7 @@
#include "qemu/module.h"
#include "sysemu/qtest.h"
#include "sysemu/tcg.h"
+#include "sysemu/kvm.h"
#include "exec/exec-all.h"
#include "cpu.h"
#include "internals.h"
@@ -21,6 +22,10 @@
#include "sysemu/reset.h"
#endif
#include "vec.h"
+#ifdef CONFIG_KVM
+#include "kvm/kvm_loongarch.h"
+#include <linux/kvm.h>
+#endif
#ifdef CONFIG_TCG
#include "exec/cpu_ldst.h"
#include "tcg/tcg.h"
@@ -113,7 +118,9 @@ void loongarch_cpu_set_irq(void *opaque, int irq, int level)
return;
}
- if (tcg_enabled()) {
+ if (kvm_enabled()) {
+ kvm_loongarch_set_interrupt(cpu, irq, level);
+ } else if (tcg_enabled()) {
env->CSR_ESTAT = deposit64(env->CSR_ESTAT, irq, 1, level != 0);
if (FIELD_EX64(env->CSR_ESTAT, CSR_ESTAT, IS)) {
cpu_interrupt(cs, CPU_INTERRUPT_HARD);
diff --git a/target/loongarch/kvm/kvm.c b/target/loongarch/kvm/kvm.c
index d2dab3fef4..bd33ec2114 100644
--- a/target/loongarch/kvm/kvm.c
+++ b/target/loongarch/kvm/kvm.c
@@ -748,6 +748,21 @@ int kvm_arch_handle_exit(CPUState *cs, struct kvm_run *run)
return ret;
}
+int kvm_loongarch_set_interrupt(LoongArchCPU *cpu, int irq, int level)
+{
+ struct kvm_interrupt intr;
+ CPUState *cs = CPU(cpu);
+
+ if (level) {
+ intr.irq = irq;
+ } else {
+ intr.irq = -irq;
+ }
+
+ trace_kvm_set_intr(irq, level);
+ return kvm_vcpu_ioctl(cs, KVM_INTERRUPT, &intr);
+}
+
void kvm_arch_accel_class_init(ObjectClass *oc)
{
}
diff --git a/target/loongarch/trace-events b/target/loongarch/trace-events
index 021839880e..dea11edc0f 100644
--- a/target/loongarch/trace-events
+++ b/target/loongarch/trace-events
@@ -12,3 +12,4 @@ kvm_failed_put_counter(const char *msg) "Failed to put counter into KVM: %s"
kvm_failed_get_cpucfg(const char *msg) "Failed to get cpucfg from KVM: %s"
kvm_failed_put_cpucfg(const char *msg) "Failed to put cpucfg into KVM: %s"
kvm_arch_handle_exit(int num) "kvm arch handle exit, the reason number: %d"
+kvm_set_intr(int irq, int level) "kvm set interrupt, irq num: %d, level: %d"
--
2.41.0
^ permalink raw reply related [flat|nested] 19+ messages in thread* Re: [PATCH v4 8/9b] target/loongarch: Implement set vcpu intr for kvm
2024-01-10 9:41 ` [PATCH v4 8/9b] target/loongarch: Implement set vcpu intr for kvm Philippe Mathieu-Daudé
@ 2024-01-11 2:29 ` gaosong
2024-01-11 8:24 ` Philippe Mathieu-Daudé
0 siblings, 1 reply; 19+ messages in thread
From: gaosong @ 2024-01-11 2:29 UTC (permalink / raw)
To: Philippe Mathieu-Daudé, qemu-devel; +Cc: Tianrui Zhao, xianglai li
Hi,
在 2024/1/10 下午5:41, Philippe Mathieu-Daudé 写道:
> From: Tianrui Zhao <zhaotianrui@loongson.cn>
>
> Implement loongarch kvm set vcpu interrupt interface,
> when a irq is set in vcpu, we use the KVM_INTERRUPT
> ioctl to set intr into kvm.
>
> Signed-off-by: Tianrui Zhao <zhaotianrui@loongson.cn>
> Signed-off-by: xianglai li <lixianglai@loongson.cn>
> Reviewed-by: Song Gao <gaosong@loongson.cn>
> Message-ID: <20240105075804.1228596-9-zhaotianrui@loongson.cn>
> [PMD: Split from bigger patch, part 2]
> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
> ---
> target/loongarch/kvm/kvm_loongarch.h | 16 ++++++++++++++++
> target/loongarch/cpu.c | 9 ++++++++-
> target/loongarch/kvm/kvm.c | 15 +++++++++++++++
> target/loongarch/trace-events | 1 +
> 4 files changed, 40 insertions(+), 1 deletion(-)
> create mode 100644 target/loongarch/kvm/kvm_loongarch.h
>
> diff --git a/target/loongarch/kvm/kvm_loongarch.h b/target/loongarch/kvm/kvm_loongarch.h
> new file mode 100644
> index 0000000000..d945b6bb82
> --- /dev/null
> +++ b/target/loongarch/kvm/kvm_loongarch.h
> @@ -0,0 +1,16 @@
> +/* SPDX-License-Identifier: GPL-2.0-or-later */
> +/*
> + * QEMU LoongArch kvm interface
> + *
> + * Copyright (c) 2023 Loongson Technology Corporation Limited
> + */
> +
> +#include "cpu.h"
> +
> +#ifndef QEMU_KVM_LOONGARCH_H
> +#define QEMU_KVM_LOONGARCH_H
> +
> +int kvm_loongarch_set_interrupt(LoongArchCPU *cpu, int irq, int level);
> +void kvm_arch_reset_vcpu(CPULoongArchState *env);
> +
> +#endif
> diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c
> index d9f8661cfd..d3a8a2f521 100644
> --- a/target/loongarch/cpu.c
> +++ b/target/loongarch/cpu.c
> @@ -12,6 +12,7 @@
> #include "qemu/module.h"
> #include "sysemu/qtest.h"
> #include "sysemu/tcg.h"
> +#include "sysemu/kvm.h"
> #include "exec/exec-all.h"
> #include "cpu.h"
> #include "internals.h"
> @@ -21,6 +22,10 @@
> #include "sysemu/reset.h"
> #endif
> #include "vec.h"
> +#ifdef CONFIG_KVM
> +#include "kvm/kvm_loongarch.h"
This broken tcg 'loongarch64-softmmu' build on X86 host, :-[
../target/loongarch/cpu.c: In function ‘loongarch_cpu_set_irq’:
../target/loongarch/cpu.c:122:9: error: implicit declaration of function
‘kvm_loongarch_set_interrupt’ [-Werror=implicit-function-declaration]
122 | kvm_loongarch_set_interrupt(cpu, irq, level);
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~
../target/loongarch/cpu.c:122:9: error: nested extern declaration of
‘kvm_loongarch_set_interrupt’ [-Werror=nested-externs]
../target/loongarch/cpu.c: In function ‘loongarch_cpu_reset_hold’:
../target/loongarch/cpu.c:557:9: error: implicit declaration of function
‘kvm_arch_reset_vcpu’; did you mean ‘kvm_arch_init_vcpu’?
[-Werror=implicit-function-declaration]
557 | kvm_arch_reset_vcpu(env);
| ^~~~~~~~~~~~~~~~~~~
| kvm_arch_init_vcpu
../target/loongarch/cpu.c:557:9: error: nested extern declaration of
‘kvm_arch_reset_vcpu’ [-Werror=nested-externs]
cc1: all warnings being treated as errors
I will move it out of '#ifdef CONFIG_KVM'
Thanks.
Song Gao
> +#include <linux/kvm.h>
> +#endif
> #ifdef CONFIG_TCG
> #include "exec/cpu_ldst.h"
> #include "tcg/tcg.h"
> @@ -113,7 +118,9 @@ void loongarch_cpu_set_irq(void *opaque, int irq, int level)
> return;
> }
>
> - if (tcg_enabled()) {
> + if (kvm_enabled()) {
> + kvm_loongarch_set_interrupt(cpu, irq, level);
> + } else if (tcg_enabled()) {
> env->CSR_ESTAT = deposit64(env->CSR_ESTAT, irq, 1, level != 0);
> if (FIELD_EX64(env->CSR_ESTAT, CSR_ESTAT, IS)) {
> cpu_interrupt(cs, CPU_INTERRUPT_HARD);
> diff --git a/target/loongarch/kvm/kvm.c b/target/loongarch/kvm/kvm.c
> index d2dab3fef4..bd33ec2114 100644
> --- a/target/loongarch/kvm/kvm.c
> +++ b/target/loongarch/kvm/kvm.c
> @@ -748,6 +748,21 @@ int kvm_arch_handle_exit(CPUState *cs, struct kvm_run *run)
> return ret;
> }
>
> +int kvm_loongarch_set_interrupt(LoongArchCPU *cpu, int irq, int level)
> +{
> + struct kvm_interrupt intr;
> + CPUState *cs = CPU(cpu);
> +
> + if (level) {
> + intr.irq = irq;
> + } else {
> + intr.irq = -irq;
> + }
> +
> + trace_kvm_set_intr(irq, level);
> + return kvm_vcpu_ioctl(cs, KVM_INTERRUPT, &intr);
> +}
> +
> void kvm_arch_accel_class_init(ObjectClass *oc)
> {
> }
> diff --git a/target/loongarch/trace-events b/target/loongarch/trace-events
> index 021839880e..dea11edc0f 100644
> --- a/target/loongarch/trace-events
> +++ b/target/loongarch/trace-events
> @@ -12,3 +12,4 @@ kvm_failed_put_counter(const char *msg) "Failed to put counter into KVM: %s"
> kvm_failed_get_cpucfg(const char *msg) "Failed to get cpucfg from KVM: %s"
> kvm_failed_put_cpucfg(const char *msg) "Failed to put cpucfg into KVM: %s"
> kvm_arch_handle_exit(int num) "kvm arch handle exit, the reason number: %d"
> +kvm_set_intr(int irq, int level) "kvm set interrupt, irq num: %d, level: %d"
^ permalink raw reply [flat|nested] 19+ messages in thread* Re: [PATCH v4 8/9b] target/loongarch: Implement set vcpu intr for kvm
2024-01-11 2:29 ` gaosong
@ 2024-01-11 8:24 ` Philippe Mathieu-Daudé
0 siblings, 0 replies; 19+ messages in thread
From: Philippe Mathieu-Daudé @ 2024-01-11 8:24 UTC (permalink / raw)
To: gaosong, qemu-devel; +Cc: Tianrui Zhao, xianglai li
On 11/1/24 03:29, gaosong wrote:
> Hi,
>
> 在 2024/1/10 下午5:41, Philippe Mathieu-Daudé 写道:
>> From: Tianrui Zhao <zhaotianrui@loongson.cn>
>>
>> Implement loongarch kvm set vcpu interrupt interface,
>> when a irq is set in vcpu, we use the KVM_INTERRUPT
>> ioctl to set intr into kvm.
>>
>> Signed-off-by: Tianrui Zhao <zhaotianrui@loongson.cn>
>> Signed-off-by: xianglai li <lixianglai@loongson.cn>
>> Reviewed-by: Song Gao <gaosong@loongson.cn>
>> Message-ID: <20240105075804.1228596-9-zhaotianrui@loongson.cn>
>> [PMD: Split from bigger patch, part 2]
>> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
>> ---
>> target/loongarch/kvm/kvm_loongarch.h | 16 ++++++++++++++++
>> target/loongarch/cpu.c | 9 ++++++++-
>> target/loongarch/kvm/kvm.c | 15 +++++++++++++++
>> target/loongarch/trace-events | 1 +
>> 4 files changed, 40 insertions(+), 1 deletion(-)
>> create mode 100644 target/loongarch/kvm/kvm_loongarch.h
>> diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c
>> index d9f8661cfd..d3a8a2f521 100644
>> --- a/target/loongarch/cpu.c
>> +++ b/target/loongarch/cpu.c
>> @@ -12,6 +12,7 @@
>> #include "qemu/module.h"
>> #include "sysemu/qtest.h"
>> #include "sysemu/tcg.h"
>> +#include "sysemu/kvm.h"
>> #include "exec/exec-all.h"
>> #include "cpu.h"
>> #include "internals.h"
>> @@ -21,6 +22,10 @@
>> #include "sysemu/reset.h"
>> #endif
>> #include "vec.h"
>> +#ifdef CONFIG_KVM
>> +#include "kvm/kvm_loongarch.h"
>
> This broken tcg 'loongarch64-softmmu' build on X86 host, :-[
>
> ../target/loongarch/cpu.c: In function ‘loongarch_cpu_set_irq’:
> ../target/loongarch/cpu.c:122:9: error: implicit declaration of function
> ‘kvm_loongarch_set_interrupt’ [-Werror=implicit-function-declaration]
> 122 | kvm_loongarch_set_interrupt(cpu, irq, level);
> | ^~~~~~~~~~~~~~~~~~~~~~~~~~~
> ../target/loongarch/cpu.c:122:9: error: nested extern declaration of
> ‘kvm_loongarch_set_interrupt’ [-Werror=nested-externs]
> ../target/loongarch/cpu.c: In function ‘loongarch_cpu_reset_hold’:
> ../target/loongarch/cpu.c:557:9: error: implicit declaration of function
> ‘kvm_arch_reset_vcpu’; did you mean ‘kvm_arch_init_vcpu’?
> [-Werror=implicit-function-declaration]
> 557 | kvm_arch_reset_vcpu(env);
> | ^~~~~~~~~~~~~~~~~~~
> | kvm_arch_init_vcpu
> ../target/loongarch/cpu.c:557:9: error: nested extern declaration of
> ‘kvm_arch_reset_vcpu’ [-Werror=nested-externs]
> cc1: all warnings being treated as errors
>
> I will move it out of '#ifdef CONFIG_KVM'
Oh, right.
(Sorry I only tested on loongarch64 host).
Thanks!
Phil.
^ permalink raw reply [flat|nested] 19+ messages in thread
* [PATCH v4 9/9] target/loongarch: Add loongarch kvm into meson build
2024-01-05 7:57 [PATCH v4 0/9] Add loongarch kvm accel support Tianrui Zhao
` (7 preceding siblings ...)
2024-01-05 7:58 ` [PATCH v4 8/9] target/loongarch: Implement set vcpu intr for kvm Tianrui Zhao
@ 2024-01-05 7:58 ` Tianrui Zhao
2024-01-10 2:36 ` gaosong
2024-01-10 2:46 ` [PATCH v4 0/9] Add loongarch kvm accel support gaosong
9 siblings, 1 reply; 19+ messages in thread
From: Tianrui Zhao @ 2024-01-05 7:58 UTC (permalink / raw)
To: qemu-devel
Cc: gaosong, maobibo, zhaotianrui, mst, cohuck, pbonzini,
marcandre.lureau, berrange, thuth, philmd, richard.henderson,
peter.maydell, yangxiaojuan, xianglai li
Add kvm.c into meson.build to compile it when kvm
is configed. Meanwhile in meson.build, we set the
kvm_targets to loongarch64-softmmu when the cpu is
loongarch. And fix the compiling error when config
is enable-kvm,disable-tcg.
Signed-off-by: Tianrui Zhao <zhaotianrui@loongson.cn>
Signed-off-by: xianglai li <lixianglai@loongson.cn>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
meson.build | 2 ++
target/loongarch/kvm/meson.build | 1 +
target/loongarch/meson.build | 1 +
3 files changed, 4 insertions(+)
create mode 100644 target/loongarch/kvm/meson.build
diff --git a/meson.build b/meson.build
index 445f2b7c2b..0c62b4156d 100644
--- a/meson.build
+++ b/meson.build
@@ -114,6 +114,8 @@ elif cpu in ['riscv32']
kvm_targets = ['riscv32-softmmu']
elif cpu in ['riscv64']
kvm_targets = ['riscv64-softmmu']
+elif cpu in ['loongarch64']
+ kvm_targets = ['loongarch64-softmmu']
else
kvm_targets = []
endif
diff --git a/target/loongarch/kvm/meson.build b/target/loongarch/kvm/meson.build
new file mode 100644
index 0000000000..2266de6ca9
--- /dev/null
+++ b/target/loongarch/kvm/meson.build
@@ -0,0 +1 @@
+loongarch_ss.add(when: 'CONFIG_KVM', if_true: files('kvm.c'))
diff --git a/target/loongarch/meson.build b/target/loongarch/meson.build
index 18e8191e2b..7f86caf373 100644
--- a/target/loongarch/meson.build
+++ b/target/loongarch/meson.build
@@ -31,3 +31,4 @@ loongarch_ss.add_all(when: 'CONFIG_TCG', if_true: [loongarch_tcg_ss])
target_arch += {'loongarch': loongarch_ss}
target_system_arch += {'loongarch': loongarch_system_ss}
+subdir('kvm')
--
2.39.1
^ permalink raw reply related [flat|nested] 19+ messages in thread* Re: [PATCH v4 9/9] target/loongarch: Add loongarch kvm into meson build
2024-01-05 7:58 ` [PATCH v4 9/9] target/loongarch: Add loongarch kvm into meson build Tianrui Zhao
@ 2024-01-10 2:36 ` gaosong
0 siblings, 0 replies; 19+ messages in thread
From: gaosong @ 2024-01-10 2:36 UTC (permalink / raw)
To: Tianrui Zhao, qemu-devel
Cc: maobibo, mst, cohuck, pbonzini, marcandre.lureau, berrange, thuth,
philmd, richard.henderson, peter.maydell, yangxiaojuan,
xianglai li
在 2024/1/5 下午3:58, Tianrui Zhao 写道:
> Add kvm.c into meson.build to compile it when kvm
> is configed. Meanwhile in meson.build, we set the
> kvm_targets to loongarch64-softmmu when the cpu is
> loongarch. And fix the compiling error when config
> is enable-kvm,disable-tcg.
>
> Signed-off-by: Tianrui Zhao <zhaotianrui@loongson.cn>
> Signed-off-by: xianglai li <lixianglai@loongson.cn>
> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
> ---
> meson.build | 2 ++
> target/loongarch/kvm/meson.build | 1 +
> target/loongarch/meson.build | 1 +
> 3 files changed, 4 insertions(+)
> create mode 100644 target/loongarch/kvm/meson.build
Reviewed-by: Song Gao <gaosong@loongson.cn>
Thanks.
Song Gao
> diff --git a/meson.build b/meson.build
> index 445f2b7c2b..0c62b4156d 100644
> --- a/meson.build
> +++ b/meson.build
> @@ -114,6 +114,8 @@ elif cpu in ['riscv32']
> kvm_targets = ['riscv32-softmmu']
> elif cpu in ['riscv64']
> kvm_targets = ['riscv64-softmmu']
> +elif cpu in ['loongarch64']Reviewed-by: Song Gao <gaosong@loongson.cn>
> + kvm_targets = ['loongarch64-softmmu']
> else
> kvm_targets = []
> endif
> diff --git a/target/loongarch/kvm/meson.build b/target/loongarch/kvm/meson.build
> new file mode 100644
> index 0000000000..2266de6ca9
> --- /dev/null
> +++ b/target/loongarch/kvm/meson.build
> @@ -0,0 +1 @@
> +loongarch_ss.add(when: 'CONFIG_KVM', if_true: files('kvm.c'))
> diff --git a/target/loongarch/meson.build b/target/loongarch/meson.build
> index 18e8191e2b..7f86caf373 100644
> --- a/target/loongarch/meson.build
> +++ b/target/loongarch/meson.build
> @@ -31,3 +31,4 @@ loongarch_ss.add_all(when: 'CONFIG_TCG', if_true: [loongarch_tcg_ss])
>
> target_arch += {'loongarch': loongarch_ss}
> target_system_arch += {'loongarch': loongarch_system_ss}
> +subdir('kvm')
^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: [PATCH v4 0/9] Add loongarch kvm accel support
2024-01-05 7:57 [PATCH v4 0/9] Add loongarch kvm accel support Tianrui Zhao
` (8 preceding siblings ...)
2024-01-05 7:58 ` [PATCH v4 9/9] target/loongarch: Add loongarch kvm into meson build Tianrui Zhao
@ 2024-01-10 2:46 ` gaosong
2024-01-10 9:42 ` Philippe Mathieu-Daudé
9 siblings, 1 reply; 19+ messages in thread
From: gaosong @ 2024-01-10 2:46 UTC (permalink / raw)
To: Tianrui Zhao, qemu-devel
Cc: maobibo, mst, cohuck, pbonzini, marcandre.lureau, berrange, thuth,
philmd, richard.henderson, peter.maydell, yangxiaojuan
在 2024/1/5 下午3:57, Tianrui Zhao 写道:
> The linux headers in this patch synchronized from linux kernel
> v6.7.0-rc8, and the loongarch kvm part of this patch series
> based on the header files. And the linux kernel has added the
> loongarch kvm support in master branch.
>
> This series add loongarch kvm support, mainly implement
> some interfaces used by kvm, such as kvm_arch_get/set_regs,
> kvm_arch_handle_exit, kvm_loongarch_set_interrupt, etc.
>
> Currently, we are able to boot LoongArch KVM Linux Guests.
> In loongarch VM, mmio devices and iocsr devices are emulated
> in user space such as APIC, IPI, pci devices, etc, other
> hardwares such as MMU, timer and csr are emulated in kernel.
>
> The running environment of LoongArch virt machine:
> 1. Get the Linux KVM environment of LoongArch in Linux mainline.
> make ARCH=loongarch CROSS_COMPILE=loongarch64-unknown-linux-gnu- loongson3_defconfig
> make ARCH=loongarch CROSS_COMPILE=loongarch64-unknown-linux-gnu-
> 2. Get the qemu source: https://github.com/loongson/qemu
> git checkout kvm-loongarch
> ./configure --target-list="loongarch64-softmmu" --enable-kvm
> make
> 3. Get uefi bios of LoongArch virt machine:
> Link: https://github.com/tianocore/edk2-platforms/tree/master/Platform/Loongson/LoongArchQemuPkg#readme
> 4. Also you can access the binary files we have already built:
> https://github.com/yangxiaojuan-loongson/qemu-binary
>
> The command to boot loongarch virt machine:
> $ qemu-system-loongarch64 -machine virt -m 4G -cpu la464 \
> -smp 1 -bios QEMU_EFI.fd -kernel vmlinuz.efi -initrd ramdisk \
> -serial stdio -monitor telnet:localhost:4495,server,nowait \
> -append "root=/dev/ram rdinit=/sbin/init console=ttyS0,115200" \
> --nographic
>
> Changes for v4:
> 1. Synchronize linux headers from linux v6.7.0-rc8.
> 2. Move kvm.c and kvm_loongarch.h into target/loongarch/kvm/
> directory.
> 3. Add "#ifndef CONFIG_USER_ONLY" before loongarch_cpu_do_interrupt
> to fix compiling issue.
> 4. Remove "#ifdef CONFIG_TCG" before "#include "exec/cpu_ldst.h""
> in fpu_helper.c, As it has been changed in other patches.
>
> Changes for v3:
> 1. Synchronize linux headers from linux v6.7.0-rc7.
> 2. Fix compiling error when config enable-kvm and disable-tcg
> at one time.
>
> Changes for v2:
> 1. Synchronize linux headers from linux v6.7.0-rc6.
> 2. Remove the stub function: kvm_loongarch_set_interrupt, as kvm_enabled
> 3. Move the kvm function such as kvm_arch_reset_vcpu from cpu.h to
> loongarch_kvm.h, and supplement "#include <cpu.h>" in loongarch_kvm.h.
>
> Changes for v1:
> 1. Synchronous KVM headers about LoongArch KVM form linux kernel,
> as the LoongArch KVM patch series have been accepted by linux kernel.
> 2. Remove the KVM_GET/SET_ONE_UREG64 macro in target/loongarch, and
> use the common interface kvm_get/set_one_reg to replace it.
> 3. Resolve the compiling errors when LoongArch is built by other archs.
>
> Tianrui Zhao (9):
> linux-headers: Synchronize linux headers from linux v6.7.0-rc8
> target/loongarch: Define some kvm_arch interfaces
> target/loongarch: Supplement vcpu env initial when vcpu reset
> target/loongarch: Implement kvm get/set registers
> target/loongarch: Implement kvm_arch_init function
> target/loongarch: Implement kvm_arch_init_vcpu
> target/loongarch: Implement kvm_arch_handle_exit
> target/loongarch: Implement set vcpu intr for kvm
> target/loongarch: Add loongarch kvm into meson build
>
> include/standard-headers/drm/drm_fourcc.h | 2 +
> include/standard-headers/linux/fuse.h | 10 +-
> include/standard-headers/linux/pci_regs.h | 24 +-
> include/standard-headers/linux/vhost_types.h | 7 +
> .../standard-headers/linux/virtio_config.h | 5 +
> include/standard-headers/linux/virtio_pci.h | 11 +
> linux-headers/asm-arm64/kvm.h | 32 +
> linux-headers/asm-generic/unistd.h | 14 +-
> linux-headers/asm-loongarch/bitsperlong.h | 1 +
> linux-headers/asm-loongarch/kvm.h | 108 +++
> linux-headers/asm-loongarch/mman.h | 1 +
> linux-headers/asm-loongarch/unistd.h | 5 +
> linux-headers/asm-mips/unistd_n32.h | 4 +
> linux-headers/asm-mips/unistd_n64.h | 4 +
> linux-headers/asm-mips/unistd_o32.h | 4 +
> linux-headers/asm-powerpc/unistd_32.h | 4 +
> linux-headers/asm-powerpc/unistd_64.h | 4 +
> linux-headers/asm-riscv/kvm.h | 12 +
> linux-headers/asm-s390/unistd_32.h | 4 +
> linux-headers/asm-s390/unistd_64.h | 4 +
> linux-headers/asm-x86/unistd_32.h | 4 +
> linux-headers/asm-x86/unistd_64.h | 3 +
> linux-headers/asm-x86/unistd_x32.h | 3 +
> linux-headers/linux/iommufd.h | 180 +++-
> linux-headers/linux/kvm.h | 11 +
> linux-headers/linux/psp-sev.h | 1 +
> linux-headers/linux/stddef.h | 9 +-
> linux-headers/linux/userfaultfd.h | 9 +-
> linux-headers/linux/vfio.h | 47 +-
> linux-headers/linux/vhost.h | 8 +
> meson.build | 3 +
> target/loongarch/cpu.c | 39 +-
> target/loongarch/cpu.h | 5 +-
> target/loongarch/internals.h | 5 +-
> target/loongarch/kvm/kvm.c | 768 ++++++++++++++++++
> target/loongarch/kvm/kvm_loongarch.h | 16 +
> target/loongarch/kvm/meson.build | 1 +
> target/loongarch/meson.build | 1 +
> target/loongarch/trace-events | 15 +
> target/loongarch/trace.h | 1 +
> 40 files changed, 1348 insertions(+), 41 deletions(-)
> create mode 100644 linux-headers/asm-loongarch/bitsperlong.h
> create mode 100644 linux-headers/asm-loongarch/kvm.h
> create mode 100644 linux-headers/asm-loongarch/mman.h
> create mode 100644 linux-headers/asm-loongarch/unistd.h
> create mode 100644 target/loongarch/kvm/kvm.c
> create mode 100644 target/loongarch/kvm/kvm_loongarch.h
> create mode 100644 target/loongarch/kvm/meson.build
> create mode 100644 target/loongarch/trace-events
> create mode 100644 target/loongarch/trace.h
>
Applied to loongarch-next.
Thanks.
Song Gao
^ permalink raw reply [flat|nested] 19+ messages in thread* Re: [PATCH v4 0/9] Add loongarch kvm accel support
2024-01-10 2:46 ` [PATCH v4 0/9] Add loongarch kvm accel support gaosong
@ 2024-01-10 9:42 ` Philippe Mathieu-Daudé
2024-01-10 10:05 ` gaosong
0 siblings, 1 reply; 19+ messages in thread
From: Philippe Mathieu-Daudé @ 2024-01-10 9:42 UTC (permalink / raw)
To: gaosong, Tianrui Zhao, qemu-devel
Cc: maobibo, mst, cohuck, pbonzini, marcandre.lureau, berrange, thuth,
richard.henderson, peter.maydell, yangxiaojuan
Hi Song,
On 10/1/24 03:46, gaosong wrote:
> 在 2024/1/5 下午3:57, Tianrui Zhao 写道:
>> This series add loongarch kvm support, mainly implement
>> some interfaces used by kvm, such as kvm_arch_get/set_regs,
>> kvm_arch_handle_exit, kvm_loongarch_set_interrupt, etc.
>> Tianrui Zhao (9):
>> linux-headers: Synchronize linux headers from linux v6.7.0-rc8
>> target/loongarch: Define some kvm_arch interfaces
>> target/loongarch: Supplement vcpu env initial when vcpu reset
>> target/loongarch: Implement kvm get/set registers
>> target/loongarch: Implement kvm_arch_init function
>> target/loongarch: Implement kvm_arch_init_vcpu
>> target/loongarch: Implement kvm_arch_handle_exit
>> target/loongarch: Implement set vcpu intr for kvm
>> target/loongarch: Add loongarch kvm into meson build
> Applied to loongarch-next.
Sorry it took me some time to test this on a loongarch64
host. I made minor changes to patch #8, please consider
the alternative:
https://lore.kernel.org/qemu-devel/20240110094152.52138-1-philmd@linaro.org/
and
https://lore.kernel.org/qemu-devel/20240110094152.52138-2-philmd@linaro.org/
^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: [PATCH v4 0/9] Add loongarch kvm accel support
2024-01-10 9:42 ` Philippe Mathieu-Daudé
@ 2024-01-10 10:05 ` gaosong
0 siblings, 0 replies; 19+ messages in thread
From: gaosong @ 2024-01-10 10:05 UTC (permalink / raw)
To: Philippe Mathieu-Daudé, Tianrui Zhao, qemu-devel
Cc: maobibo, mst, cohuck, pbonzini, marcandre.lureau, berrange, thuth,
richard.henderson, peter.maydell, yangxiaojuan
在 2024/1/10 下午5:42, Philippe Mathieu-Daudé 写道:
> Hi Song,
>
> On 10/1/24 03:46, gaosong wrote:
>> 在 2024/1/5 下午3:57, Tianrui Zhao 写道:
>
>>> This series add loongarch kvm support, mainly implement
>>> some interfaces used by kvm, such as kvm_arch_get/set_regs,
>>> kvm_arch_handle_exit, kvm_loongarch_set_interrupt, etc.
>
>
>>> Tianrui Zhao (9):
>>> linux-headers: Synchronize linux headers from linux v6.7.0-rc8
>>> target/loongarch: Define some kvm_arch interfaces
>>> target/loongarch: Supplement vcpu env initial when vcpu reset
>>> target/loongarch: Implement kvm get/set registers
>>> target/loongarch: Implement kvm_arch_init function
>>> target/loongarch: Implement kvm_arch_init_vcpu
>>> target/loongarch: Implement kvm_arch_handle_exit
>>> target/loongarch: Implement set vcpu intr for kvm
>>> target/loongarch: Add loongarch kvm into meson build
>
>
>> Applied to loongarch-next.
>
> Sorry it took me some time to test this on a loongarch64
> host. I made minor changes to patch #8, please consider
> the alternative:
> https://lore.kernel.org/qemu-devel/20240110094152.52138-1-philmd@linaro.org/
> and
> https://lore.kernel.org/qemu-devel/20240110094152.52138-2-philmd@linaro.org/
>
Thank you , I wll apply them to loongarch-next.
if no new problem with this series, I think we can merge it on this week.
Thanks.
Song Gao
^ permalink raw reply [flat|nested] 19+ messages in thread