[PATCH 0/4] i386/cpu: Clean Up Reserved CPUID Leaves for Intel

[PATCH 0/4] i386/cpu: Clean Up Reserved CPUID Leaves for Intel

[Zhao Liu]

Hi,

Since the previsor unified cache model series has already introduced a
new compat property "x-vendor-cpuid-only-v2", it's a chance to once
again consolidate more vendor-specific CPUIDs.

I also checked the CPUID leaves currently supported by Intel & AMD and
found that since the previous "x-vendor-cpuid-only," AMD has already
cleaned up the Intel-specific CPUIDs quite well.

As for Intel, the only cleanup needed is for the "extended function
CPUID" leaves (0x80000000~0x80000008). That's what this series does.

This series is based on:

<20250626083105.2581859-1-zhao1.liu@intel.com>

Or you can find the code at:

https://gitlab.com/zhao.liu/qemu/-/tree/cache-model-v2.6-rebase-06-23-2025

Thanks and Best Regards,
Zhao
---
Zhao Liu (4):
  i386/cpu: Mark EBX/ECX/EDX in CPUID 0x80000000 leaf as reserved for
    Intel
  i386/cpu: Mark CPUID 0x80000007[EBX] as reserved for Intel
  i386/cpu: Mark ECX/EDX in CPUID 0x80000008 leaf as reserved for Intel
  i386/cpu: Reorder CPUID leaves in cpu_x86_cpuid()

 target/i386/cpu.c | 83 ++++++++++++++++++++++++++++-------------------
 1 file changed, 49 insertions(+), 34 deletions(-)

-- 
2.34.1

[PATCH 1/4] i386/cpu: Mark EBX/ECX/EDX in CPUID 0x80000000 leaf as reserved for Intel

[Zhao Liu]

Per SDM,

80000000H EAX Maximum Input Value for Extended Function CPUID Information.
          EBX Reserved.
          ECX Reserved.
          EDX Reserved.

EBX/ECX/EDX in CPUID 0x80000000 leaf are reserved. Intel is using 0x0
leaf to encode vendor.

Signed-off-by: Zhao Liu <zhao1.liu@intel.com>
---
 target/i386/cpu.c | 11 ++++++++---
 1 file changed, 8 insertions(+), 3 deletions(-)

diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index c7f157a0f71c..867e08236540 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -8280,9 +8280,14 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count,
         break;
     case 0x80000000:
         *eax = env->cpuid_xlevel;
-        *ebx = env->cpuid_vendor1;
-        *edx = env->cpuid_vendor2;
-        *ecx = env->cpuid_vendor3;
+
+        if (cpu->vendor_cpuid_only_v2 && IS_INTEL_CPU(env)) {
+            *ebx = *ecx = *edx = 0;
+        } else {
+            *ebx = env->cpuid_vendor1;
+            *edx = env->cpuid_vendor2;
+            *ecx = env->cpuid_vendor3;
+        }
         break;
     case 0x80000001:
         *eax = env->cpuid_version;
-- 
2.34.1

Re: [PATCH 1/4] i386/cpu: Mark EBX/ECX/EDX in CPUID 0x80000000 leaf as reserved for Intel

[Ewan Hai]

On 6/27/25 11:51 AM, Zhao Liu wrote:
> +        if (cpu->vendor_cpuid_only_v2 && IS_INTEL_CPU(env)) {

Please also add IS_ZHAOXIN_CPU(env), since Zhaoxin follows the SDM definition 
for CPUID leaf 0x80000000.

> +            *ebx = *ecx = *edx = 0;
> +        } else {
> +            *ebx = env->cpuid_vendor1;
> +            *edx = env->cpuid_vendor2;
> +            *ecx = env->cpuid_vendor3;
> +        }

Re: [PATCH 1/4] i386/cpu: Mark EBX/ECX/EDX in CPUID 0x80000000 leaf as reserved for Intel

[Xiaoyao Li]

On 6/27/2025 11:51 AM, Zhao Liu wrote:
> Per SDM,
> 
> 80000000H EAX Maximum Input Value for Extended Function CPUID Information.
>            EBX Reserved.
>            ECX Reserved.
>            EDX Reserved.
> 
> EBX/ECX/EDX in CPUID 0x80000000 leaf are reserved. Intel is using 0x0
> leaf to encode vendor.
> 
> Signed-off-by: Zhao Liu <zhao1.liu@intel.com>
> ---
>   target/i386/cpu.c | 11 ++++++++---
>   1 file changed, 8 insertions(+), 3 deletions(-)
> 
> diff --git a/target/i386/cpu.c b/target/i386/cpu.c
> index c7f157a0f71c..867e08236540 100644
> --- a/target/i386/cpu.c
> +++ b/target/i386/cpu.c
> @@ -8280,9 +8280,14 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count,
>           break;
>       case 0x80000000:
>           *eax = env->cpuid_xlevel;
> -        *ebx = env->cpuid_vendor1;
> -        *edx = env->cpuid_vendor2;
> -        *ecx = env->cpuid_vendor3;
> +
> +        if (cpu->vendor_cpuid_only_v2 && IS_INTEL_CPU(env)) {
> +            *ebx = *ecx = *edx = 0;

"Reserved" is different to "Reserved to 0".

So you'd better provide justification like "set them to all zero as what 
real Intel processor returns"

> +        } else {
> +            *ebx = env->cpuid_vendor1;
> +            *edx = env->cpuid_vendor2;
> +            *ecx = env->cpuid_vendor3;
> +        }
>           break;
>       case 0x80000001:
>           *eax = env->cpuid_version;

[PATCH 2/4] i386/cpu: Mark CPUID 0x80000007[EBX] as reserved for Intel

[Zhao Liu]

Per SDM,

80000007H EAX Reserved = 0.
          EBX Reserved = 0.
          ECX Reserved = 0.
          EDX Bits 07-00: Reserved = 0.
              Bit 08: Invariant TSC available if 1.
              Bits 31-09: Reserved = 0.

EAX/EBX/ECX in CPUID 0x80000007 leaf are reserved for Intel.

At present, EAX is reserved for AMD, too. And AMD hasn't used ECX in
QEMU. So these 2 registers are both left as 0.

Therefore, only fix the EBX and excode it as 0 for Intel.

Signed-off-by: Zhao Liu <zhao1.liu@intel.com>
---
 target/i386/cpu.c | 6 +++++-
 1 file changed, 5 insertions(+), 1 deletion(-)

diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index 867e08236540..6d590a9af389 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -8374,7 +8374,11 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count,
     }
     case 0x80000007:
         *eax = 0;
-        *ebx = env->features[FEAT_8000_0007_EBX];
+        if (cpu->vendor_cpuid_only_v2 && IS_INTEL_CPU(env)) {
+            *ebx = 0;
+        } else {
+            *ebx = env->features[FEAT_8000_0007_EBX];
+        }
         *ecx = 0;
         *edx = env->features[FEAT_8000_0007_EDX];
         break;
-- 
2.34.1

Re: [PATCH 2/4] i386/cpu: Mark CPUID 0x80000007[EBX] as reserved for Intel

[Ewan Hai]

On 6/27/25 11:51 AM, Zhao Liu wrote:
> 
> Per SDM,
> 
> 80000007H EAX Reserved = 0.
>            EBX Reserved = 0.
>            ECX Reserved = 0.
>            EDX Bits 07-00: Reserved = 0.
>                Bit 08: Invariant TSC available if 1.
>                Bits 31-09: Reserved = 0.
> 
> EAX/EBX/ECX in CPUID 0x80000007 leaf are reserved for Intel.
> 
> At present, EAX is reserved for AMD, too. And AMD hasn't used ECX in
> QEMU. So these 2 registers are both left as 0.
> 
> Therefore, only fix the EBX and excode it as 0 for Intel.
> 
> Signed-off-by: Zhao Liu <zhao1.liu@intel.com>
> ---
>   target/i386/cpu.c | 6 +++++-
>   1 file changed, 5 insertions(+), 1 deletion(-)
> 
> diff --git a/target/i386/cpu.c b/target/i386/cpu.c
> index 867e08236540..6d590a9af389 100644
> --- a/target/i386/cpu.c
> +++ b/target/i386/cpu.c
> @@ -8374,7 +8374,11 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count,
>       }
>       case 0x80000007:
>           *eax = 0;
> -        *ebx = env->features[FEAT_8000_0007_EBX];
> +        if (cpu->vendor_cpuid_only_v2 && IS_INTEL_CPU(env)) {

Please add IS_ZHAOXIN_CPU(env), because Zhaoxin follows the SDM definition for 
CPUID leaf 0x80000008.

> +            *ebx = 0;
> +        } else {
> +            *ebx = env->features[FEAT_8000_0007_EBX];
> +        }
>           *ecx = 0;
>           *edx = env->features[FEAT_8000_0007_EDX];
>           break;
> --
> 2.34.1
> 

[PATCH 3/4] i386/cpu: Mark ECX/EDX in CPUID 0x80000008 leaf as reserved for Intel

[Zhao Liu]

Per SDM,

80000008H EAX Linear/Physical Address size.
              Bits 07-00: #Physical Address Bits*.
              Bits 15-08: #Linear Address Bits.
              Bits 31-16: Reserved = 0.
          EBX Bits 08-00: Reserved = 0.
              Bit 09: WBNOINVD is available if 1.
              Bits 31-10: Reserved = 0.
          ECX Reserved = 0.
          EDX Reserved = 0.

ECX/EDX in CPUID 0x80000008 leaf are reserved. Encode these 2 registers
as 0 for Intel.

Signed-off-by: Zhao Liu <zhao1.liu@intel.com>
---
 target/i386/cpu.c | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index 6d590a9af389..5d5a227d4c8a 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -8391,6 +8391,12 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count,
              *eax |= (cpu->guest_phys_bits << 16);
         }
         *ebx = env->features[FEAT_8000_0008_EBX];
+
+        if (cpu->vendor_cpuid_only_v2 && IS_INTEL_CPU(env)) {
+            *ecx = *edx = 0;
+            break;
+        }
+
         if (threads_per_pkg > 1) {
             /*
              * Bits 15:12 is "The number of bits in the initial
-- 
2.34.1

Re: [PATCH 3/4] i386/cpu: Mark ECX/EDX in CPUID 0x80000008 leaf as reserved for Intel

[Ewan Hai]

On 6/27/25 11:51 AM, Zhao Liu wrote:
> 
> 
> Per SDM,
> 
> 80000008H EAX Linear/Physical Address size.
>                Bits 07-00: #Physical Address Bits*.
>                Bits 15-08: #Linear Address Bits.
>                Bits 31-16: Reserved = 0.
>            EBX Bits 08-00: Reserved = 0.
>                Bit 09: WBNOINVD is available if 1.
>                Bits 31-10: Reserved = 0.
>            ECX Reserved = 0.
>            EDX Reserved = 0.
> 
> ECX/EDX in CPUID 0x80000008 leaf are reserved. Encode these 2 registers
> as 0 for Intel.
> 
> Signed-off-by: Zhao Liu <zhao1.liu@intel.com>
> ---
>   target/i386/cpu.c | 6 ++++++
>   1 file changed, 6 insertions(+)
> 
> diff --git a/target/i386/cpu.c b/target/i386/cpu.c
> index 6d590a9af389..5d5a227d4c8a 100644
> --- a/target/i386/cpu.c
> +++ b/target/i386/cpu.c
> @@ -8391,6 +8391,12 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count,
>                *eax |= (cpu->guest_phys_bits << 16);
>           }
>           *ebx = env->features[FEAT_8000_0008_EBX];
> +
> +        if (cpu->vendor_cpuid_only_v2 && IS_INTEL_CPU(env)) {

Please add IS_ZHAOXIN_CPU(env), Zhaoxin follow SDM's definition on cpuid leaf 
0x8000_0008.

> +            *ecx = *edx = 0;
> +            break;
> +        }
> +
>           if (threads_per_pkg > 1) {
>               /*
>                * Bits 15:12 is "The number of bits in the initial
> --
> 2.34.1
> 

Re: [PATCH 3/4] i386/cpu: Mark ECX/EDX in CPUID 0x80000008 leaf as reserved for Intel

[Xiaoyao Li]

On 6/27/2025 11:51 AM, Zhao Liu wrote:
> Per SDM,
> 
> 80000008H EAX Linear/Physical Address size.
>                Bits 07-00: #Physical Address Bits*.
>                Bits 15-08: #Linear Address Bits.
>                Bits 31-16: Reserved = 0.
>            EBX Bits 08-00: Reserved = 0.
>                Bit 09: WBNOINVD is available if 1.
>                Bits 31-10: Reserved = 0.
>            ECX Reserved = 0.
>            EDX Reserved = 0.
> 
> ECX/EDX in CPUID 0x80000008 leaf are reserved. Encode these 2 registers
> as 0 for Intel.
> 
> Signed-off-by: Zhao Liu <zhao1.liu@intel.com>
> ---
>   target/i386/cpu.c | 6 ++++++
>   1 file changed, 6 insertions(+)
> 
> diff --git a/target/i386/cpu.c b/target/i386/cpu.c
> index 6d590a9af389..5d5a227d4c8a 100644
> --- a/target/i386/cpu.c
> +++ b/target/i386/cpu.c
> @@ -8391,6 +8391,12 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count,
>                *eax |= (cpu->guest_phys_bits << 16);
>           }
>           *ebx = env->features[FEAT_8000_0008_EBX];
> +
> +        if (cpu->vendor_cpuid_only_v2 && IS_INTEL_CPU(env)) {
> +            *ecx = *edx = 0;
> +            break;
> +        }

current code guarantees ecx and edx to be 0 for !IS_AMD_CPU(). I think 
the patch is unnecessary.

>           if (threads_per_pkg > 1) {
>               /*
>                * Bits 15:12 is "The number of bits in the initial

Re: [PATCH 3/4] i386/cpu: Mark ECX/EDX in CPUID 0x80000008 leaf as reserved for Intel

[Zhao Liu]

> > +        if (cpu->vendor_cpuid_only_v2 && IS_INTEL_CPU(env)) {
> > +            *ecx = *edx = 0;
> > +            break;
> > +        }
> 
> current code guarantees ecx and edx to be 0 for !IS_AMD_CPU(). I think the
> patch is unnecessary.

Hi, could you please tell me why?

Thanks,
Zhao

> >           if (threads_per_pkg > 1) {
> >               /*
> >                * Bits 15:12 is "The number of bits in the initial
> 

Re: [PATCH 3/4] i386/cpu: Mark ECX/EDX in CPUID 0x80000008 leaf as reserved for Intel

[Xiaoyao Li]

On 6/30/2025 1:20 PM, Zhao Liu wrote:
>>> +        if (cpu->vendor_cpuid_only_v2 && IS_INTEL_CPU(env)) {
>>> +            *ecx = *edx = 0;
>>> +            break;
>>> +        }
>>
>> current code guarantees ecx and edx to be 0 for !IS_AMD_CPU(). I think the
>> patch is unnecessary.
> 
> Hi, could you please tell me why?

Sorry that I was looking at the wrong branch, which has my previous 
patch of 
https://lore.kernel.org/qemu-devel/20240814075431.339209-7-xiaoyao.li@intel.com/

My patch isn't merged and you patch is not unnecessary.

Sorry again.

> Thanks,
> Zhao
> 
>>>            if (threads_per_pkg > 1) {
>>>                /*
>>>                 * Bits 15:12 is "The number of bits in the initial
>>

[PATCH 4/4] i386/cpu: Reorder CPUID leaves in cpu_x86_cpuid()

[Zhao Liu]

Sort the CPUID leaves strictly by index to facilitate checking and
changing.

Signed-off-by: Zhao Liu <zhao1.liu@intel.com>
---
 target/i386/cpu.c | 60 +++++++++++++++++++++++------------------------
 1 file changed, 30 insertions(+), 30 deletions(-)

diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index 5d5a227d4c8a..18bb0e9cf9f6 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -8052,21 +8052,6 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count,
         assert(!(*eax & ~0x1f));
         *ebx &= 0xffff; /* The count doesn't need to be reliable. */
         break;
-    case 0x1C:
-        if (cpu->enable_pmu && (env->features[FEAT_7_0_EDX] & CPUID_7_0_EDX_ARCH_LBR)) {
-            x86_cpu_get_supported_cpuid(0x1C, 0, eax, ebx, ecx, edx);
-            *edx = 0;
-        }
-        break;
-    case 0x1F:
-        /* V2 Extended Topology Enumeration Leaf */
-        if (!x86_has_cpuid_0x1f(cpu)) {
-            *eax = *ebx = *ecx = *edx = 0;
-            break;
-        }
-
-        encode_topo_cpuid1f(env, count, topo_info, eax, ebx, ecx, edx);
-        break;
     case 0xD: {
         /* Processor Extended State */
         *eax = 0;
@@ -8207,6 +8192,12 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count,
         }
         break;
     }
+    case 0x1C:
+        if (cpu->enable_pmu && (env->features[FEAT_7_0_EDX] & CPUID_7_0_EDX_ARCH_LBR)) {
+            x86_cpu_get_supported_cpuid(0x1C, 0, eax, ebx, ecx, edx);
+            *edx = 0;
+        }
+        break;
     case 0x1D: {
         /* AMX TILE, for now hardcoded for Sapphire Rapids*/
         *eax = 0;
@@ -8244,6 +8235,15 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count,
         }
         break;
     }
+    case 0x1F:
+        /* V2 Extended Topology Enumeration Leaf */
+        if (!x86_has_cpuid_0x1f(cpu)) {
+            *eax = *ebx = *ecx = *edx = 0;
+            break;
+        }
+
+        encode_topo_cpuid1f(env, count, topo_info, eax, ebx, ecx, edx);
+        break;
     case 0x24: {
         *eax = 0;
         *ebx = 0;
@@ -8465,6 +8465,21 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count,
             *edx = 0;
         }
         break;
+    case 0x8000001F:
+        *eax = *ebx = *ecx = *edx = 0;
+        if (sev_enabled()) {
+            *eax = 0x2;
+            *eax |= sev_es_enabled() ? 0x8 : 0;
+            *eax |= sev_snp_enabled() ? 0x10 : 0;
+            *ebx = sev_get_cbit_position() & 0x3f; /* EBX[5:0] */
+            *ebx |= (sev_get_reduced_phys_bits() & 0x3f) << 6; /* EBX[11:6] */
+        }
+        break;
+    case 0x80000021:
+        *eax = *ebx = *ecx = *edx = 0;
+        *eax = env->features[FEAT_8000_0021_EAX];
+        *ebx = env->features[FEAT_8000_0021_EBX];
+        break;
     case 0x80000022:
         *eax = *ebx = *ecx = *edx = 0;
         /* AMD Extended Performance Monitoring and Debug */
@@ -8497,21 +8512,6 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count,
         *ecx = 0;
         *edx = 0;
         break;
-    case 0x8000001F:
-        *eax = *ebx = *ecx = *edx = 0;
-        if (sev_enabled()) {
-            *eax = 0x2;
-            *eax |= sev_es_enabled() ? 0x8 : 0;
-            *eax |= sev_snp_enabled() ? 0x10 : 0;
-            *ebx = sev_get_cbit_position() & 0x3f; /* EBX[5:0] */
-            *ebx |= (sev_get_reduced_phys_bits() & 0x3f) << 6; /* EBX[11:6] */
-        }
-        break;
-    case 0x80000021:
-        *eax = *ebx = *ecx = *edx = 0;
-        *eax = env->features[FEAT_8000_0021_EAX];
-        *ebx = env->features[FEAT_8000_0021_EBX];
-        break;
     default:
         /* reserved values: zero */
         *eax = 0;
-- 
2.34.1

Re: [PATCH 0/4] i386/cpu: Clean Up Reserved CPUID Leaves for Intel

[Xiaoyao Li]

On 6/27/2025 11:51 AM, Zhao Liu wrote:
> Hi,
> 
> Since the previsor unified cache model series has already introduced a
> new compat property "x-vendor-cpuid-only-v2", it's a chance to once
> again consolidate more vendor-specific CPUIDs.

Please provide the link to the patch that introduced 
"x-vendor-cpuid-only-v2"

When talking about vendor-specific CPUIDs, there are multiple vendors 
for x86, including Intel, AMD, Hygon and Zhaoxin. From the patches, you 
are only dealing with Intel specifically. So a basic question is, why 
not rename "x-vendor-cpuid-only-v2" to "x-intel-cpuid-only"?


> I also checked the CPUID leaves currently supported by Intel & AMD and
> found that since the previous "x-vendor-cpuid-only," AMD has already
> cleaned up the Intel-specific CPUIDs quite well.
> 
> As for Intel, the only cleanup needed is for the "extended function
> CPUID" leaves (0x80000000~0x80000008). That's what this series does.
> 
> This series is based on:
> 
> <20250626083105.2581859-1-zhao1.liu@intel.com>
> 
> Or you can find the code at:
> 
> https://gitlab.com/zhao.liu/qemu/-/tree/cache-model-v2.6-rebase-06-23-2025
> 
> Thanks and Best Regards,
> Zhao
> ---
> Zhao Liu (4):
>    i386/cpu: Mark EBX/ECX/EDX in CPUID 0x80000000 leaf as reserved for
>      Intel
>    i386/cpu: Mark CPUID 0x80000007[EBX] as reserved for Intel
>    i386/cpu: Mark ECX/EDX in CPUID 0x80000008 leaf as reserved for Intel
>    i386/cpu: Reorder CPUID leaves in cpu_x86_cpuid()
> 
>   target/i386/cpu.c | 83 ++++++++++++++++++++++++++++-------------------
>   1 file changed, 49 insertions(+), 34 deletions(-)
> 

Re: [PATCH 0/4] i386/cpu: Clean Up Reserved CPUID Leaves for Intel

[Tao Su]

On Fri, Jun 27, 2025 at 11:51:25AM +0800, Zhao Liu wrote:
> Hi,
> 
> Since the previsor unified cache model series has already introduced a
> new compat property "x-vendor-cpuid-only-v2", it's a chance to once
> again consolidate more vendor-specific CPUIDs.
> 
> I also checked the CPUID leaves currently supported by Intel & AMD and
> found that since the previous "x-vendor-cpuid-only," AMD has already
> cleaned up the Intel-specific CPUIDs quite well.
> 
> As for Intel, the only cleanup needed is for the "extended function
> CPUID" leaves (0x80000000~0x80000008). That's what this series does.
> 
> This series is based on:
> 
> <20250626083105.2581859-1-zhao1.liu@intel.com>
> 
> Or you can find the code at:
> 
> https://gitlab.com/zhao.liu/qemu/-/tree/cache-model-v2.6-rebase-06-23-2025

For the whole series,

Reviewed-by: Tao Su <tao1.su@linux.intel.com>

> 
> Thanks and Best Regards,
> Zhao
> ---
> Zhao Liu (4):
>   i386/cpu: Mark EBX/ECX/EDX in CPUID 0x80000000 leaf as reserved for
>     Intel
>   i386/cpu: Mark CPUID 0x80000007[EBX] as reserved for Intel
>   i386/cpu: Mark ECX/EDX in CPUID 0x80000008 leaf as reserved for Intel
>   i386/cpu: Reorder CPUID leaves in cpu_x86_cpuid()
> 
>  target/i386/cpu.c | 83 ++++++++++++++++++++++++++++-------------------
>  1 file changed, 49 insertions(+), 34 deletions(-)
> 
> -- 
> 2.34.1
> 
>