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[83.53.161.74]) by smtp.gmail.com with ESMTPSA id v4sm1829803wml.46.2020.09.30.03.25.29 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 30 Sep 2020 03:25:30 -0700 (PDT) Subject: Re: [PATCH RFC 14/14] target/: fix some comment spelling errors To: zhaolichang , qemu-trivial@nongnu.org References: <20200930095321.2006-1-zhaolichang@huawei.com> <20200930095321.2006-15-zhaolichang@huawei.com> From: =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= Message-ID: Date: Wed, 30 Sep 2020 12:25:29 +0200 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.11.0 MIME-Version: 1.0 In-Reply-To: <20200930095321.2006-15-zhaolichang@huawei.com> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::444; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-x444.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -15 X-Spam_score: -1.6 X-Spam_bar: - X-Spam_report: (-1.6 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.25, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.199, NICE_REPLY_A=-0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On 9/30/20 11:53 AM, zhaolichang wrote: > I found that there are many spelling errors in the comments of qemu/target. > I used spellcheck to check the spelling errors and found some errors in the folder. > > Signed-off-by: zhaolichang Reviewed-by: Philippe Mathieu-Daudé > --- > target/openrisc/cpu.h | 2 +- > target/sparc/asi.h | 2 +- > target/unicore32/translate.c | 2 +- > 3 files changed, 3 insertions(+), 3 deletions(-) > > diff --git a/target/openrisc/cpu.h b/target/openrisc/cpu.h > index bd42faf..8ca8605 100644 > --- a/target/openrisc/cpu.h > +++ b/target/openrisc/cpu.h > @@ -291,7 +291,7 @@ typedef struct CPUOpenRISCState { > int is_counting; > > uint32_t picmr; /* Interrupt mask register */ > - uint32_t picsr; /* Interrupt contrl register*/ > + uint32_t picsr; /* Interrupt control register*/ > #endif > void *irq[32]; /* Interrupt irq input */ > } CPUOpenRISCState; > diff --git a/target/sparc/asi.h b/target/sparc/asi.h > index bb58735..4e9f1d5 100644 > --- a/target/sparc/asi.h > +++ b/target/sparc/asi.h > @@ -231,7 +231,7 @@ > #define ASI_INTR_ID 0x63 /* (CMT) Interrupt ID register */ > #define ASI_CORE_ID 0x63 /* (CMT) LP ID register */ > #define ASI_CESR_ID 0x63 /* (CMT) CESR ID register */ > -#define ASI_IC_INSTR 0x66 /* Insn cache instrucion ram diag */ > +#define ASI_IC_INSTR 0x66 /* Insn cache instruction ram diag */ > #define ASI_IC_TAG 0x67 /* Insn cache tag/valid ram diag */ > #define ASI_IC_STAG 0x68 /* (III) Insn cache snoop tag ram */ > #define ASI_IC_PRE_DECODE 0x6e /* Insn cache pre-decode ram diag */ > diff --git a/target/unicore32/translate.c b/target/unicore32/translate.c > index d4b06df..2e91b05 100644 > --- a/target/unicore32/translate.c > +++ b/target/unicore32/translate.c > @@ -119,7 +119,7 @@ static void load_reg_var(DisasContext *s, TCGv var, int reg) > { > if (reg == 31) { > uint32_t addr; > - /* normaly, since we updated PC */ > + /* normally, since we updated PC */ > addr = (long)s->pc; > tcg_gen_movi_i32(var, addr); > } else { >