* [PATCH v2 0/2] tcg: ppc64: Fix mask generation for vextractdm
@ 2023-05-04 9:35 Shivaprasad G Bhat
2023-05-04 9:35 ` [PATCH v2 1/2] " Shivaprasad G Bhat
` (2 more replies)
0 siblings, 3 replies; 6+ messages in thread
From: Shivaprasad G Bhat @ 2023-05-04 9:35 UTC (permalink / raw)
To: philmd, richard.henderson, danielhb413, lucas.araujo, qemu-ppc,
clg, david, groug, qemu-ppc
Cc: john_platts, sbhat, qemu-devel
While debugging gitlab issue[1] 1536, I happen to try the
vextract[X]m instructions on the real hardware. The test
used in [1] is failing for vextractdm.
On debugging it is seen, in function do_extractm() the
mask is calculated as dup_const(1 << (element_width - 1)).
'1' being signed int works fine for MO_8,16,32. For MO_64,
on PPC64 host this ends up becoming 0 on compilation. The
vextractdm uses MO_64, and it ends up having mask as 0.
The first patch here fixes that by explicitly using
1ULL instead of signed int 1 like its used everywhere else.
Second patch introduces the test case from [1] into qemu
tcg/ppc64 along with fixes/tweaks to make it work for both
big and little-endian targets.
References:
[1] : https://gitlab.com/qemu-project/qemu/-/issues/1536
---
Changelog:
Since v1 : https://lists.gnu.org/archive/html/qemu-devel/2023-04/msg01958.html
- Added "Resolves: " to first patch description
- Rebased to top of the tree. I see with d044b7c33a5, Alex has limited the
scope of plugin tests to just the MULTIARCH_TESTS. So, removed the plugin
tests for the test case added in the second patch.
- Changed the test case to use the HOST_BIG_ENDIAN from compiler.h
Shivaprasad G Bhat (2):
tcg: ppc64: Fix mask generation for vextractdm
tests: tcg: ppc64: Add tests for Vector Extract Mask Instructions
target/ppc/translate/vmx-impl.c.inc | 2 +-
tests/tcg/ppc64/Makefile.target | 6 +++-
tests/tcg/ppc64/vector.c | 51 +++++++++++++++++++++++++++++
3 files changed, 57 insertions(+), 2 deletions(-)
create mode 100644 tests/tcg/ppc64/vector.c
--
Signature
^ permalink raw reply [flat|nested] 6+ messages in thread* [PATCH v2 1/2] tcg: ppc64: Fix mask generation for vextractdm 2023-05-04 9:35 [PATCH v2 0/2] tcg: ppc64: Fix mask generation for vextractdm Shivaprasad G Bhat @ 2023-05-04 9:35 ` Shivaprasad G Bhat 2023-05-04 6:20 ` Cédric Le Goater 2023-05-04 9:36 ` [PATCH v2 2/2] tests: tcg: ppc64: Add tests for Vector Extract Mask Instructions Shivaprasad G Bhat 2023-05-04 11:06 ` [PATCH v2 0/2] tcg: ppc64: Fix mask generation for vextractdm Daniel Henrique Barboza 2 siblings, 1 reply; 6+ messages in thread From: Shivaprasad G Bhat @ 2023-05-04 9:35 UTC (permalink / raw) To: philmd, richard.henderson, danielhb413, lucas.araujo, qemu-ppc, clg, david, groug, qemu-ppc Cc: john_platts, sbhat, qemu-devel In function do_extractm() the mask is calculated as dup_const(1 << (element_width - 1)). '1' being signed int works fine for MO_8,16,32. For MO_64, on PPC64 host this ends up becoming 0 on compilation. The vextractdm uses MO_64, and it ends up having mask as 0. Explicitly use 1ULL instead of signed int 1 like its used everywhere else. Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1536 Signed-off-by: Shivaprasad G Bhat <sbhat@linux.ibm.com> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Lucas Mateus Castro <lucas.araujo@eldorado.org.br> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> --- target/ppc/translate/vmx-impl.c.inc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/ppc/translate/vmx-impl.c.inc b/target/ppc/translate/vmx-impl.c.inc index 112233b541..c8712dd7d8 100644 --- a/target/ppc/translate/vmx-impl.c.inc +++ b/target/ppc/translate/vmx-impl.c.inc @@ -2058,7 +2058,7 @@ static bool trans_VEXPANDQM(DisasContext *ctx, arg_VX_tb *a) static bool do_vextractm(DisasContext *ctx, arg_VX_tb *a, unsigned vece) { const uint64_t elem_width = 8 << vece, elem_count_half = 8 >> vece, - mask = dup_const(vece, 1 << (elem_width - 1)); + mask = dup_const(vece, 1ULL << (elem_width - 1)); uint64_t i, j; TCGv_i64 lo, hi, t0, t1; ^ permalink raw reply related [flat|nested] 6+ messages in thread
* Re: [PATCH v2 1/2] tcg: ppc64: Fix mask generation for vextractdm 2023-05-04 9:35 ` [PATCH v2 1/2] " Shivaprasad G Bhat @ 2023-05-04 6:20 ` Cédric Le Goater 0 siblings, 0 replies; 6+ messages in thread From: Cédric Le Goater @ 2023-05-04 6:20 UTC (permalink / raw) To: Shivaprasad G Bhat, philmd, richard.henderson, danielhb413, lucas.araujo, qemu-ppc, david, groug Cc: john_platts, qemu-devel On 5/4/23 11:35, Shivaprasad G Bhat wrote: > In function do_extractm() the mask is calculated as > dup_const(1 << (element_width - 1)). '1' being signed int > works fine for MO_8,16,32. For MO_64, on PPC64 host > this ends up becoming 0 on compilation. The vextractdm > uses MO_64, and it ends up having mask as 0. > > Explicitly use 1ULL instead of signed int 1 like its > used everywhere else. > > Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1536 > Signed-off-by: Shivaprasad G Bhat <sbhat@linux.ibm.com> > Reviewed-by: Alex Bennée <alex.bennee@linaro.org> > Reviewed-by: Lucas Mateus Castro <lucas.araujo@eldorado.org.br> > Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Cédric Le Goater <clg@redhat.com> Thanks, C. > --- > target/ppc/translate/vmx-impl.c.inc | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/target/ppc/translate/vmx-impl.c.inc b/target/ppc/translate/vmx-impl.c.inc > index 112233b541..c8712dd7d8 100644 > --- a/target/ppc/translate/vmx-impl.c.inc > +++ b/target/ppc/translate/vmx-impl.c.inc > @@ -2058,7 +2058,7 @@ static bool trans_VEXPANDQM(DisasContext *ctx, arg_VX_tb *a) > static bool do_vextractm(DisasContext *ctx, arg_VX_tb *a, unsigned vece) > { > const uint64_t elem_width = 8 << vece, elem_count_half = 8 >> vece, > - mask = dup_const(vece, 1 << (elem_width - 1)); > + mask = dup_const(vece, 1ULL << (elem_width - 1)); > uint64_t i, j; > TCGv_i64 lo, hi, t0, t1; > > > ^ permalink raw reply [flat|nested] 6+ messages in thread
* [PATCH v2 2/2] tests: tcg: ppc64: Add tests for Vector Extract Mask Instructions 2023-05-04 9:35 [PATCH v2 0/2] tcg: ppc64: Fix mask generation for vextractdm Shivaprasad G Bhat 2023-05-04 9:35 ` [PATCH v2 1/2] " Shivaprasad G Bhat @ 2023-05-04 9:36 ` Shivaprasad G Bhat 2023-05-04 6:22 ` Cédric Le Goater 2023-05-04 11:06 ` [PATCH v2 0/2] tcg: ppc64: Fix mask generation for vextractdm Daniel Henrique Barboza 2 siblings, 1 reply; 6+ messages in thread From: Shivaprasad G Bhat @ 2023-05-04 9:36 UTC (permalink / raw) To: philmd, richard.henderson, danielhb413, lucas.araujo, qemu-ppc, clg, david, groug, qemu-ppc Cc: john_platts, sbhat, qemu-devel Add test for vextractbm, vextractwm, vextractdm and vextractqm instructions. Test works for both qemu-ppc64 and qemu-ppc64le. Based on the test case written by John Platts posted at [1] References: [1] - https://gitlab.com/qemu-project/qemu/-/issues/1536 Signed-off-by: John Platts <john_platts@hotmail.com> Signed-off-by: Shivaprasad G Bhat <sbhat@linux.ibm.com> Reviewed-by: Lucas Mateus Castro <lucas.araujo@eldorado.org.br> --- tests/tcg/ppc64/Makefile.target | 5 +++- tests/tcg/ppc64/vector.c | 51 +++++++++++++++++++++++++++++++++++++++ 2 files changed, 55 insertions(+), 1 deletion(-) create mode 100644 tests/tcg/ppc64/vector.c diff --git a/tests/tcg/ppc64/Makefile.target b/tests/tcg/ppc64/Makefile.target index 6d47d3cae6..b084963b9a 100644 --- a/tests/tcg/ppc64/Makefile.target +++ b/tests/tcg/ppc64/Makefile.target @@ -20,7 +20,7 @@ PPC64_TESTS += mtfsf PPC64_TESTS += mffsce ifneq ($(CROSS_CC_HAS_POWER10),) -PPC64_TESTS += byte_reverse sha512-vector +PPC64_TESTS += byte_reverse sha512-vector vector endif byte_reverse: CFLAGS += -mcpu=power10 run-byte_reverse: QEMU_OPTS+=-cpu POWER10 @@ -31,6 +31,9 @@ sha512-vector: sha512.c run-sha512-vector: QEMU_OPTS+=-cpu POWER10 +vector: CFLAGS += -mcpu=power10 -I$(SRC_PATH)/include +run-vector: QEMU_OPTS += -cpu POWER10 + PPC64_TESTS += signal_save_restore_xer PPC64_TESTS += xxspltw diff --git a/tests/tcg/ppc64/vector.c b/tests/tcg/ppc64/vector.c new file mode 100644 index 0000000000..cbf4ae9332 --- /dev/null +++ b/tests/tcg/ppc64/vector.c @@ -0,0 +1,51 @@ +#include <assert.h> +#include <stdint.h> +#include "qemu/compiler.h" + +int main(void) +{ + unsigned int result_wi; + vector unsigned char vbc_bi_src = { 0xFF, 0xFF, 0, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0, 0, 0, + 0, 0xFF, 0xFF}; + vector unsigned short vbc_hi_src = { 0xFFFF, 0, 0, 0xFFFF, + 0, 0, 0xFFFF, 0xFFFF}; + vector unsigned int vbc_wi_src = {0, 0, 0xFFFFFFFF, 0xFFFFFFFF}; + vector unsigned long long vbc_di_src = {0xFFFFFFFFFFFFFFFF, 0}; + vector __uint128_t vbc_qi_src; + + asm("vextractbm %0, %1" : "=r" (result_wi) : "v" (vbc_bi_src)); +#if HOST_BIG_ENDIAN + assert(result_wi == 0b1101111111000011); +#else + assert(result_wi == 0b1100001111111011); +#endif + + asm("vextracthm %0, %1" : "=r" (result_wi) : "v" (vbc_hi_src)); +#if HOST_BIG_ENDIAN + assert(result_wi == 0b10010011); +#else + assert(result_wi == 0b11001001); +#endif + + asm("vextractwm %0, %1" : "=r" (result_wi) : "v" (vbc_wi_src)); +#if HOST_BIG_ENDIAN + assert(result_wi == 0b0011); +#else + assert(result_wi == 0b1100); +#endif + + asm("vextractdm %0, %1" : "=r" (result_wi) : "v" (vbc_di_src)); +#if HOST_BIG_ENDIAN + assert(result_wi == 0b10); +#else + assert(result_wi == 0b01); +#endif + + vbc_qi_src[0] = 0x1; + vbc_qi_src[0] = vbc_qi_src[0] << 127; + asm("vextractqm %0, %1" : "=r" (result_wi) : "v" (vbc_qi_src)); + assert(result_wi == 0b1); + + return 0; +} ^ permalink raw reply related [flat|nested] 6+ messages in thread
* Re: [PATCH v2 2/2] tests: tcg: ppc64: Add tests for Vector Extract Mask Instructions 2023-05-04 9:36 ` [PATCH v2 2/2] tests: tcg: ppc64: Add tests for Vector Extract Mask Instructions Shivaprasad G Bhat @ 2023-05-04 6:22 ` Cédric Le Goater 0 siblings, 0 replies; 6+ messages in thread From: Cédric Le Goater @ 2023-05-04 6:22 UTC (permalink / raw) To: Shivaprasad G Bhat, philmd, richard.henderson, danielhb413, lucas.araujo, qemu-ppc, david, groug Cc: john_platts, qemu-devel On 5/4/23 11:36, Shivaprasad G Bhat wrote: > Add test for vextractbm, vextractwm, vextractdm and vextractqm > instructions. Test works for both qemu-ppc64 and qemu-ppc64le. > > Based on the test case written by John Platts posted at [1] > > References: > [1] - https://gitlab.com/qemu-project/qemu/-/issues/1536 > > Signed-off-by: John Platts <john_platts@hotmail.com> > Signed-off-by: Shivaprasad G Bhat <sbhat@linux.ibm.com> > Reviewed-by: Lucas Mateus Castro <lucas.araujo@eldorado.org.br> Reviewed-by: Cédric Le Goater <clg@redhat.com> Thanks, C. > --- > tests/tcg/ppc64/Makefile.target | 5 +++- > tests/tcg/ppc64/vector.c | 51 +++++++++++++++++++++++++++++++++++++++ > 2 files changed, 55 insertions(+), 1 deletion(-) > create mode 100644 tests/tcg/ppc64/vector.c > > diff --git a/tests/tcg/ppc64/Makefile.target b/tests/tcg/ppc64/Makefile.target > index 6d47d3cae6..b084963b9a 100644 > --- a/tests/tcg/ppc64/Makefile.target > +++ b/tests/tcg/ppc64/Makefile.target > @@ -20,7 +20,7 @@ PPC64_TESTS += mtfsf > PPC64_TESTS += mffsce > > ifneq ($(CROSS_CC_HAS_POWER10),) > -PPC64_TESTS += byte_reverse sha512-vector > +PPC64_TESTS += byte_reverse sha512-vector vector > endif > byte_reverse: CFLAGS += -mcpu=power10 > run-byte_reverse: QEMU_OPTS+=-cpu POWER10 > @@ -31,6 +31,9 @@ sha512-vector: sha512.c > > run-sha512-vector: QEMU_OPTS+=-cpu POWER10 > > +vector: CFLAGS += -mcpu=power10 -I$(SRC_PATH)/include > +run-vector: QEMU_OPTS += -cpu POWER10 > + > PPC64_TESTS += signal_save_restore_xer > PPC64_TESTS += xxspltw > > diff --git a/tests/tcg/ppc64/vector.c b/tests/tcg/ppc64/vector.c > new file mode 100644 > index 0000000000..cbf4ae9332 > --- /dev/null > +++ b/tests/tcg/ppc64/vector.c > @@ -0,0 +1,51 @@ > +#include <assert.h> > +#include <stdint.h> > +#include "qemu/compiler.h" > + > +int main(void) > +{ > + unsigned int result_wi; > + vector unsigned char vbc_bi_src = { 0xFF, 0xFF, 0, 0xFF, 0xFF, 0xFF, > + 0xFF, 0xFF, 0xFF, 0xFF, 0, 0, 0, > + 0, 0xFF, 0xFF}; > + vector unsigned short vbc_hi_src = { 0xFFFF, 0, 0, 0xFFFF, > + 0, 0, 0xFFFF, 0xFFFF}; > + vector unsigned int vbc_wi_src = {0, 0, 0xFFFFFFFF, 0xFFFFFFFF}; > + vector unsigned long long vbc_di_src = {0xFFFFFFFFFFFFFFFF, 0}; > + vector __uint128_t vbc_qi_src; > + > + asm("vextractbm %0, %1" : "=r" (result_wi) : "v" (vbc_bi_src)); > +#if HOST_BIG_ENDIAN > + assert(result_wi == 0b1101111111000011); > +#else > + assert(result_wi == 0b1100001111111011); > +#endif > + > + asm("vextracthm %0, %1" : "=r" (result_wi) : "v" (vbc_hi_src)); > +#if HOST_BIG_ENDIAN > + assert(result_wi == 0b10010011); > +#else > + assert(result_wi == 0b11001001); > +#endif > + > + asm("vextractwm %0, %1" : "=r" (result_wi) : "v" (vbc_wi_src)); > +#if HOST_BIG_ENDIAN > + assert(result_wi == 0b0011); > +#else > + assert(result_wi == 0b1100); > +#endif > + > + asm("vextractdm %0, %1" : "=r" (result_wi) : "v" (vbc_di_src)); > +#if HOST_BIG_ENDIAN > + assert(result_wi == 0b10); > +#else > + assert(result_wi == 0b01); > +#endif > + > + vbc_qi_src[0] = 0x1; > + vbc_qi_src[0] = vbc_qi_src[0] << 127; > + asm("vextractqm %0, %1" : "=r" (result_wi) : "v" (vbc_qi_src)); > + assert(result_wi == 0b1); > + > + return 0; > +} > > ^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH v2 0/2] tcg: ppc64: Fix mask generation for vextractdm 2023-05-04 9:35 [PATCH v2 0/2] tcg: ppc64: Fix mask generation for vextractdm Shivaprasad G Bhat 2023-05-04 9:35 ` [PATCH v2 1/2] " Shivaprasad G Bhat 2023-05-04 9:36 ` [PATCH v2 2/2] tests: tcg: ppc64: Add tests for Vector Extract Mask Instructions Shivaprasad G Bhat @ 2023-05-04 11:06 ` Daniel Henrique Barboza 2 siblings, 0 replies; 6+ messages in thread From: Daniel Henrique Barboza @ 2023-05-04 11:06 UTC (permalink / raw) To: Shivaprasad G Bhat, philmd, richard.henderson, lucas.araujo, qemu-ppc, clg, david, groug Cc: john_platts, qemu-devel Queued in gitlab.com/danielhb/qemu/tree/ppc-next. Thanks, Daniel On 5/4/23 06:35, Shivaprasad G Bhat wrote: > While debugging gitlab issue[1] 1536, I happen to try the > vextract[X]m instructions on the real hardware. The test > used in [1] is failing for vextractdm. > > On debugging it is seen, in function do_extractm() the > mask is calculated as dup_const(1 << (element_width - 1)). > '1' being signed int works fine for MO_8,16,32. For MO_64, > on PPC64 host this ends up becoming 0 on compilation. The > vextractdm uses MO_64, and it ends up having mask as 0. > > The first patch here fixes that by explicitly using > 1ULL instead of signed int 1 like its used everywhere else. > Second patch introduces the test case from [1] into qemu > tcg/ppc64 along with fixes/tweaks to make it work for both > big and little-endian targets. > > References: > [1] : https://gitlab.com/qemu-project/qemu/-/issues/1536 > > --- > Changelog: > Since v1 : https://lists.gnu.org/archive/html/qemu-devel/2023-04/msg01958.html > - Added "Resolves: " to first patch description > - Rebased to top of the tree. I see with d044b7c33a5, Alex has limited the > scope of plugin tests to just the MULTIARCH_TESTS. So, removed the plugin > tests for the test case added in the second patch. > - Changed the test case to use the HOST_BIG_ENDIAN from compiler.h > > Shivaprasad G Bhat (2): > tcg: ppc64: Fix mask generation for vextractdm > tests: tcg: ppc64: Add tests for Vector Extract Mask Instructions > > > target/ppc/translate/vmx-impl.c.inc | 2 +- > tests/tcg/ppc64/Makefile.target | 6 +++- > tests/tcg/ppc64/vector.c | 51 +++++++++++++++++++++++++++++ > 3 files changed, 57 insertions(+), 2 deletions(-) > create mode 100644 tests/tcg/ppc64/vector.c > > -- > Signature > ^ permalink raw reply [flat|nested] 6+ messages in thread
end of thread, other threads:[~2023-05-04 11:06 UTC | newest] Thread overview: 6+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2023-05-04 9:35 [PATCH v2 0/2] tcg: ppc64: Fix mask generation for vextractdm Shivaprasad G Bhat 2023-05-04 9:35 ` [PATCH v2 1/2] " Shivaprasad G Bhat 2023-05-04 6:20 ` Cédric Le Goater 2023-05-04 9:36 ` [PATCH v2 2/2] tests: tcg: ppc64: Add tests for Vector Extract Mask Instructions Shivaprasad G Bhat 2023-05-04 6:22 ` Cédric Le Goater 2023-05-04 11:06 ` [PATCH v2 0/2] tcg: ppc64: Fix mask generation for vextractdm Daniel Henrique Barboza
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