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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3912bfdfdc5sm13058383f8f.25.2025.03.09.18.32.52 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Sun, 09 Mar 2025 18:32:52 -0700 (PDT) Message-ID: Date: Mon, 10 Mar 2025 02:32:51 +0100 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH] hw/net/smc91c111: Don't allow data register access to overrun buffer To: Peter Maydell , qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: qemu-stable@nongnu.org References: <20250228191652.1957208-1-peter.maydell@linaro.org> Content-Language: en-US From: =?UTF-8?Q?Philippe_Mathieu-Daud=C3=A9?= In-Reply-To: <20250228191652.1957208-1-peter.maydell@linaro.org> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::430; envelope-from=philmd@linaro.org; helo=mail-wr1-x430.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On 28/2/25 20:16, Peter Maydell wrote: > For accesses to the 91c111 data register, the address within the > packet's data frame is determined by a combination of the pointer > register and the offset used to access the data register, so that you > can access data at effectively wider than byte width. The pointer > register's pointer field is 11 bits wide, which is exactly the size > to index a 2048-byte data frame. > > We weren't quite getting the logic right for ensuring that we end up > with a pointer value to use in the s->data[][] array that isn't out > of bounds: > > * we correctly mask when getting the initial pointer value > * for the "autoincrement the pointer register" case, we > correctly mask after adding 1 so that the pointer register > wraps back around at the 2048 byte mark > * but for the non-autoincrement case where we have to add the > low 2 bits of the data register offset, we don't account > for the possibility that the pointer register is 0x7ff > and the addition should wrap > > Fix this bug by factoring out the "get the p value to use as an array > index" into a function, making it use FIELD macro names rather than > hard-coded constants, and having a utility function that does "add a > value and wrap it" that we can use both for the "autoincrement" and > "add the offset bits" codepaths. > > Cc: qemu-stable@nongnu.org > Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2758 > Signed-off-by: Peter Maydell > --- > Based-on: 20250228174802.1945417-1-peter.maydell@linaro.org > ("hw/net/smc91c111: Fix potential array overflows") > > I'd only just sent the other smc91c111 patchset when I found > another fuzzer bug for it in the bug tracker :-) > > The "modernisation" of the code seemed clearer to me than > doing a minimal in-place fix (which would look something > like "p = (p + (offset & 3) & 0x7ff;" in both read and write > functions). But it does make the actual bugfix a little less > obvious. > > --- > hw/net/smc91c111.c | 65 +++++++++++++++++++++++++++++++++++++--------- > 1 file changed, 53 insertions(+), 12 deletions(-) Well clean, thanks. Reviewed-by: Philippe Mathieu-Daudé