Re: [PATCH v4 02/12] tcg/riscv: Add basic support for vector

[LIU Zhiwei <zhiwei_liu@linux.alibaba.com>]

On 2024/9/18 18:11, Richard Henderson wrote:
> On 9/18/24 07:17, LIU Zhiwei wrote:
>>
>> On 2024/9/12 2:41, Richard Henderson wrote:
>>> On 9/11/24 06:26, LIU Zhiwei wrote:
>>>> From: Swung0x48<swung0x48@outlook.com>
>>>>
>>>> The RISC-V vector instruction set utilizes the LMUL field to group
>>>> multiple registers, enabling variable-length vector registers. This
>>>> implementation uses only the first register number of each group while
>>>> reserving the other register numbers within the group.
>>>>
>>>> In TCG, each VEC_IR can have 3 types (TCG_TYPE_V64/128/256), and the
>>>> host runtime needs to adjust LMUL based on the type to use different
>>>> register groups.
>>>>
>>>> This presents challenges for TCG's register allocation. Currently, we
>>>> avoid modifying the register allocation part of TCG and only expose 
>>>> the
>>>> minimum number of vector registers.
>>>>
>>>> For example, when the host vlen is 64 bits and type is 
>>>> TCG_TYPE_V256, with
>>>> LMUL equal to 4, we use 4 vector registers as one register group. 
>>>> We can
>>>> use a maximum of 8 register groups, but the V0 register number is 
>>>> reserved
>>>> as a mask register, so we can effectively use at most 7 register 
>>>> groups.
>>>> Moreover, when type is smaller than TCG_TYPE_V256, only 7 registers 
>>>> are
>>>> forced to be used. This is because TCG cannot yet dynamically 
>>>> constrain
>>>> registers with type; likewise, when the host vlen is 128 bits and
>>>> TCG_TYPE_V256, we can use at most 15 registers.
>>>>
>>>> There is not much pressure on vector register allocation in TCG 
>>>> now, so
>>>> using 7 registers is feasible and will not have a major impact on code
>>>> generation.
>>>>
>>>> This patch:
>>>> 1. Reserves vector register 0 for use as a mask register.
>>>> 2. When using register groups, reserves the additional registers 
>>>> within
>>>>     each group.
>>>>
>>>> Signed-off-by: TANG Tiancheng<tangtiancheng.ttc@alibaba-inc.com>
>>>> Co-authored-by: TANG Tiancheng<tangtiancheng.ttc@alibaba-inc.com>
>>>
>>> If there is a co-author, there should be another Signed-off-by.
>>
>> This patch has added a tag:
>>
>> Signed-off-by: TANG Tiancheng<tangtiancheng.ttc@alibaba-inc.com>
>>
>>
>> Do you mean we should add the same tag twice?
>
> The from line is "Swung0x48 <swung0x48@outlook.com>".
> If this is an alternate email for TANG Tiancheng,

No, Swung0x48 is another author.

Thanks,
Zhiwei

> then please fix the patch --author.
>
>
> r~