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From: Richard Henderson <richard.henderson@linaro.org>
To: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>, qemu-devel@nongnu.org
Cc: qemu-riscv@nongnu.org, palmer@dabbelt.com,
	alistair.francis@wdc.com, dbarboza@ventanamicro.com,
	liwei1518@gmail.com, bmeng.cn@gmail.com
Subject: Re: [PATCH v3 2/3] target/riscv: Add MXLEN check for F/D/Q applies to zama16b
Date: Fri, 2 Aug 2024 17:54:17 +1000	[thread overview]
Message-ID: <b8f126b8-feb9-415f-8bf6-6ad874f38f48@linaro.org> (raw)
In-Reply-To: <20240802072417.659-3-zhiwei_liu@linux.alibaba.com>

On 8/2/24 17:24, LIU Zhiwei wrote:
> Zama16b loads and stores of no more than MXLEN bits defined in the F, D, and Q
> extensions.
> 
> Signed-off-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
> ---
>   target/riscv/insn_trans/trans_rvd.c.inc | 8 ++++++--
>   1 file changed, 6 insertions(+), 2 deletions(-)
> 
> diff --git a/target/riscv/insn_trans/trans_rvd.c.inc b/target/riscv/insn_trans/trans_rvd.c.inc
> index 0ac42c3223..49682292b8 100644
> --- a/target/riscv/insn_trans/trans_rvd.c.inc
> +++ b/target/riscv/insn_trans/trans_rvd.c.inc
> @@ -47,7 +47,11 @@ static bool trans_fld(DisasContext *ctx, arg_fld *a)
>       REQUIRE_FPU;
>       REQUIRE_EXT(ctx, RVD);
>   
> -    if (ctx->cfg_ptr->ext_zama16b) {
> +    /*
> +     * Zama16b applies to loads and stores of no more than MXLEN bits defined
> +     * in the F, D, and Q extensions.
> +     */
> +    if ((get_xl_max(ctx) >= MXL_RV64) && ctx->cfg_ptr->ext_zama16b) {
>           memop |= MO_ATOM_WITHIN16;
>       }
>   
> @@ -67,7 +71,7 @@ static bool trans_fsd(DisasContext *ctx, arg_fsd *a)
>       REQUIRE_FPU;
>       REQUIRE_EXT(ctx, RVD);
>   
> -    if (ctx->cfg_ptr->ext_zama16b) {
> +    if ((get_xl_max(ctx) >= MXL_RV64) && ctx->cfg_ptr->ext_zama16b) {
>           memop |= MO_ATOM_WITHIN16;
>       }
>   

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>

r~


  reply	other threads:[~2024-08-02  7:54 UTC|newest]

Thread overview: 11+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2024-08-02  7:24 [PATCH v3 0/3] target/riscv: Remove redundant insn length check for zama16b LIU Zhiwei
2024-08-02  7:24 ` [PATCH v3 1/3] " LIU Zhiwei
2024-08-02  7:53   ` Richard Henderson
2024-08-04 23:52   ` Alistair Francis
2024-08-02  7:24 ` [PATCH v3 2/3] target/riscv: Add MXLEN check for F/D/Q applies to zama16b LIU Zhiwei
2024-08-02  7:54   ` Richard Henderson [this message]
2024-08-04 23:54   ` Alistair Francis
2024-08-02  7:24 ` [PATCH v3 3/3] target/riscv: Relax fld alignment requirement LIU Zhiwei
2024-08-02  7:54   ` Richard Henderson
2024-08-04 23:56   ` Alistair Francis
2024-08-05  1:51 ` [PATCH v3 0/3] target/riscv: Remove redundant insn length check for zama16b Alistair Francis

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