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Tue, 09 Sep 2025 06:37:57 -0700 (PDT) X-Google-Smtp-Source: AGHT+IEQeixLWcTdEbly64R52FEdqYxYew4FhKB2D2VCtNgzmJUAbRKYc+KCWcQLQrdZhaIEkL8diw== X-Received: by 2002:a05:600c:840f:b0:45b:6365:794e with SMTP id 5b1f17b1804b1-45dddecdacemr113680545e9.24.1757425077341; Tue, 09 Sep 2025 06:37:57 -0700 (PDT) Received: from [192.168.43.95] ([37.167.152.186]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-45df15cac87sm10478285e9.2.2025.09.09.06.37.54 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 09 Sep 2025 06:37:56 -0700 (PDT) Message-ID: Date: Tue, 9 Sep 2025 15:37:53 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [RFC PATCH v3 07/15] hw/arm/smmuv3: Implement get_viommu_cap() callback Content-Language: en-US To: Jason Gunthorpe , Shameer Kolothum Cc: "qemu-arm@nongnu.org" , "qemu-devel@nongnu.org" , "peter.maydell@linaro.org" , Nicolin Chen , "ddutile@redhat.com" , "berrange@redhat.com" , Nathan Chen , Matt Ochs , "smostafa@google.com" , "linuxarm@huawei.com" , "wangzhou1@hisilicon.com" , "jiangkunkun@huawei.com" , "jonathan.cameron@huawei.com" , "zhangfei.gao@linaro.org" , "zhenzhong.duan@intel.com" , "shameerkolothum@gmail.com" References: <20250714155941.22176-1-shameerali.kolothum.thodi@huawei.com> <20250714155941.22176-8-shameerali.kolothum.thodi@huawei.com> <20250908134030.GG616306@nvidia.com> From: Eric Auger In-Reply-To: <20250908134030.GG616306@nvidia.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=170.10.129.124; envelope-from=eric.auger@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H5=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-To: eric.auger@redhat.com Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Hi Jason, Shameer, On 9/8/25 3:40 PM, Jason Gunthorpe wrote: > On Mon, Sep 08, 2025 at 08:22:59AM +0000, Shameer Kolothum wrote: >>> nit: strictly speaking couldn't we have a stage2 being used at guest >>> level implemented by a stage1 at physical level? >>> but it is totally fair to restrict the support. >> Yeah it is possible I guess. But then we have to use the S2TTB to configure >> Host SMMUv3 S1 instead of S1ContextPtr which is used now. > S1 and S2 have different PTE formats, you cannot take a guest S2 table > with S2 PTEs and have the hypervisor program it to a S1. > > The guest must see a SMMU with no S2 support in the IDRs. Yes you're right. As PTE are different we cannot do it. Sorry for the noise. Eric > > Jason >