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From: Richard Henderson <richard.henderson@linaro.org>
To: John Arbuckle <programmingkidx@gmail.com>,
	qemu-devel@nongnu.org, qemu-ppc@nongnu.org, rth@twiddle.net,
	david@gibson.dropbear.id.au
Subject: Re: [Qemu-devel] [PATCH] Implement Fraction Rounded bit in FPSCR for PowerPC
Date: Tue, 21 May 2019 23:30:31 -0400	[thread overview]
Message-ID: <b90278ec-ee66-76c6-32b5-d5aca1fb8d24@linaro.org> (raw)
In-Reply-To: <20190522000617.21945-1-programmingkidx@gmail.com>

On 5/21/19 8:06 PM, John Arbuckle wrote:
> Implement the PowerPC floating point status and control register flag Fraction Rounded.
> 
> Signed-off-by: John Arbuckle <programmingkidx@gmail.com>
> ---
>  fpu/softfloat.c               | 15 ++++++++++++---
>  include/fpu/softfloat-types.h |  1 +
>  target/ppc/fpu_helper.c       |  4 ++++
>  3 files changed, 17 insertions(+), 3 deletions(-)

Please split the target/ppc part away from the softfloat part.

Also, we should note that there are more places within softfloat that need to
be adjusted so that float_float_rounded is fully supported.


r~


  reply	other threads:[~2019-05-22  3:31 UTC|newest]

Thread overview: 4+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-05-22  0:06 [Qemu-devel] [PATCH] Implement Fraction Rounded bit in FPSCR for PowerPC John Arbuckle
2019-05-22  3:30 ` Richard Henderson [this message]
2019-05-22 15:25   ` G 3
2019-05-22 15:41     ` Richard Henderson

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