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X-Received-From: 2607:f8b0:4864:20::c41 Subject: Re: [Qemu-devel] [PATCH] Implement Fraction Rounded bit in FPSCR for PowerPC X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On 5/21/19 8:06 PM, John Arbuckle wrote: > Implement the PowerPC floating point status and control register flag Fraction Rounded. > > Signed-off-by: John Arbuckle > --- > fpu/softfloat.c | 15 ++++++++++++--- > include/fpu/softfloat-types.h | 1 + > target/ppc/fpu_helper.c | 4 ++++ > 3 files changed, 17 insertions(+), 3 deletions(-) Please split the target/ppc part away from the softfloat part. Also, we should note that there are more places within softfloat that need to be adjusted so that float_float_rounded is fully supported. r~