[Qemu-devel] [PATCH] Implement Fraction Rounded bit in FPSCR for PowerPC

[Qemu-devel] [PATCH] Implement Fraction Rounded bit in FPSCR for PowerPC

[John Arbuckle]

Implement the PowerPC floating point status and control register flag Fraction Rounded.

Signed-off-by: John Arbuckle <programmingkidx@gmail.com>
---
 fpu/softfloat.c               | 15 ++++++++++++---
 include/fpu/softfloat-types.h |  1 +
 target/ppc/fpu_helper.c       |  4 ++++
 3 files changed, 17 insertions(+), 3 deletions(-)

diff --git a/fpu/softfloat.c b/fpu/softfloat.c
index 2ba36ec370..ac34f6a2de 100644
--- a/fpu/softfloat.c
+++ b/fpu/softfloat.c
@@ -702,7 +702,7 @@ static FloatParts round_canonical(FloatParts p, float_status *s,
     const uint64_t roundeven_mask = parm->roundeven_mask;
     const int exp_max = parm->exp_max;
     const int frac_shift = parm->frac_shift;
-    uint64_t frac, inc;
+    uint64_t frac, inc, rounded;
     int exp, flags = 0;
     bool overflow_norm;
 
@@ -744,7 +744,12 @@ static FloatParts round_canonical(FloatParts p, float_status *s,
         if (likely(exp > 0)) {
             if (frac & round_mask) {
                 flags |= float_flag_inexact;
-                frac += inc;
+                rounded = frac + inc;
+                if ((rounded ^ frac) & frac_lsb) {
+                    flags |= float_flag_rounded;
+                }
+                frac = rounded;
+
                 if (frac & DECOMPOSED_OVERFLOW_BIT) {
                     frac >>= 1;
                     exp++;
@@ -793,7 +798,11 @@ static FloatParts round_canonical(FloatParts p, float_status *s,
                     break;
                 }
                 flags |= float_flag_inexact;
-                frac += inc;
+                rounded = frac + inc;
+                if ((rounded ^ frac) & frac_lsb) {
+                    flags |= float_flag_rounded;
+                }
+                frac = rounded;
             }
 
             exp = (frac & DECOMPOSED_IMPLICIT_BIT ? 1 : 0);
diff --git a/include/fpu/softfloat-types.h b/include/fpu/softfloat-types.h
index 2aae6a89b1..bee576e0fd 100644
--- a/include/fpu/softfloat-types.h
+++ b/include/fpu/softfloat-types.h
@@ -147,6 +147,7 @@ enum {
 
 enum {
     float_flag_invalid   =  1,
+    float_flag_rounded   =  2,
     float_flag_divbyzero =  4,
     float_flag_overflow  =  8,
     float_flag_underflow = 16,
diff --git a/target/ppc/fpu_helper.c b/target/ppc/fpu_helper.c
index 0b7308f539..0baf1ce8e4 100644
--- a/target/ppc/fpu_helper.c
+++ b/target/ppc/fpu_helper.c
@@ -630,6 +630,10 @@ static void do_float_check_status(CPUPPCState *env, uintptr_t raddr)
         env->fpscr &= ~(1 << FPSCR_FI); /* clear the FPSCR[FI] bit */
     }
 
+    /* Set or clear the Fraction Rounded bit */
+    env->fpscr = deposit32(env->fpscr, FPSCR_FR, 1,
+                           (status & float_flag_rounded) != 0);
+
     if (cs->exception_index == POWERPC_EXCP_PROGRAM &&
         (env->error_code & POWERPC_EXCP_FP)) {
         /* Differred floating-point exception after target FPR update */
-- 
2.14.3 (Apple Git-98)

Re: [Qemu-devel] [PATCH] Implement Fraction Rounded bit in FPSCR for PowerPC

[Richard Henderson]

On 5/21/19 8:06 PM, John Arbuckle wrote:
> Implement the PowerPC floating point status and control register flag Fraction Rounded.
> 
> Signed-off-by: John Arbuckle <programmingkidx@gmail.com>
> ---
>  fpu/softfloat.c               | 15 ++++++++++++---
>  include/fpu/softfloat-types.h |  1 +
>  target/ppc/fpu_helper.c       |  4 ++++
>  3 files changed, 17 insertions(+), 3 deletions(-)

Please split the target/ppc part away from the softfloat part.

Also, we should note that there are more places within softfloat that need to
be adjusted so that float_float_rounded is fully supported.


r~

Re: [Qemu-devel] [PATCH] Implement Fraction Rounded bit in FPSCR for PowerPC

[G 3]

Thank you for the suggestion.

For the added note, did you want specific places listed? If so please let
me know these places.

Thank you.

On Tue, May 21, 2019 at 11:30 PM Richard Henderson <
richard.henderson@linaro.org> wrote:

> On 5/21/19 8:06 PM, John Arbuckle wrote:
> > Implement the PowerPC floating point status and control register flag
> Fraction Rounded.
> >
> > Signed-off-by: John Arbuckle <programmingkidx@gmail.com>
> > ---
> >  fpu/softfloat.c               | 15 ++++++++++++---
> >  include/fpu/softfloat-types.h |  1 +
> >  target/ppc/fpu_helper.c       |  4 ++++
> >  3 files changed, 17 insertions(+), 3 deletions(-)
>
> Please split the target/ppc part away from the softfloat part.
>
> Also, we should note that there are more places within softfloat that need
> to
> be adjusted so that float_float_rounded is fully supported.
>
>
> r~
>

Re: [Qemu-devel] [PATCH] Implement Fraction Rounded bit in FPSCR for PowerPC

[Richard Henderson]

On 5/22/19 11:25 AM, G 3 wrote:
> Thank you for the suggestion.
> 
> For the added note, did you want specific places listed? If so please let me
> know these places.
> 

They are round_to_int, and all of the legacy roundAndPack* routines.
Basically anywhere that currently sets float_flag_inexact.


r~