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[173.198.77.92]) by smtp.gmail.com with ESMTPSA id y14sm45642908pfe.147.2020.01.22.00.53.30 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 22 Jan 2020 00:53:31 -0800 (PST) Subject: Re: [PATCH] riscv: Format Rd of FMV.W.X with NoN-boxing To: Ian Jiang , qemu-devel@nongnu.org References: <20200122072448.18510-1-ianjiang.ict@gmail.com> From: Richard Henderson Message-ID: Date: Tue, 21 Jan 2020 22:53:27 -1000 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.4.1 MIME-Version: 1.0 In-Reply-To: <20200122072448.18510-1-ianjiang.ict@gmail.com> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 7bit X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::1043 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: palmer@dabbelt.com, Alistair.Francis@wdc.com, sagark@eecs.berkeley.edu, kbastian@mail.uni-paderborn.de Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On 1/21/20 9:24 PM, Ian Jiang wrote: > For FMV.W.X that moves the lower 32 bits of an integer register to a > floating-point register, Rd should encoded with NoN-boxing scheme. > Note: This applies to RV64 only. > > Signed-off-by: Ian Jiang > --- > target/riscv/insn_trans/trans_rvf.inc.c | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/target/riscv/insn_trans/trans_rvf.inc.c b/target/riscv/insn_trans/trans_rvf.inc.c > index 172dbfa919..62b7a36567 100644 > --- a/target/riscv/insn_trans/trans_rvf.inc.c > +++ b/target/riscv/insn_trans/trans_rvf.inc.c > @@ -368,6 +368,7 @@ static bool trans_fmv_w_x(DisasContext *ctx, arg_fmv_w_x *a) > > #if defined(TARGET_RISCV64) > tcg_gen_mov_i64(cpu_fpr[a->rd], t0); > + tcg_gen_ori_i64(cpu_fpr[a->rd], cpu_fpr[a->rd], 0xffffffff00000000ULL); > #else > tcg_gen_extu_i32_i64(cpu_fpr[a->rd], t0); > #endif > This doesn't look right. There's nothing in the spec that says the nan-boxing is restricted to rv64. NaN-boxing is all about FLEN, not XLEN. r~