From: Richard Henderson <richard.henderson@linaro.org>
To: Song Gao <gaosong@loongson.cn>, qemu-devel@nongnu.org
Cc: philmd@linaro.org, maobibo@loongson.cn, yangxiaojuan@loongson.cn
Subject: Re: [PATCH 3/3] hw/loongarch/virt: Set max 256 cpus support on loongarch virt machine
Date: Wed, 10 May 2023 11:12:12 +0100 [thread overview]
Message-ID: <b9152ff5-b17f-11b0-6aa0-e7a002885ccf@linaro.org> (raw)
In-Reply-To: <0d391c88-6749-b1c3-466b-e90d91ada360@loongson.cn>
On 4/26/23 02:37, Song Gao wrote:
> ping~
>
> 在 2023/4/6 下午6:00, Song Gao 写道:
>> Add separate macro EXTIOI_CPUS for extioi interrupt controller, extioi
>> only supports 4 cpu. And set macro LOONGARCH_MAX_CPUS as 256 so that
>> loongarch virt machine supports more cpus.
>>
>> Interrupts from external devices can only be routed cpu 0-3 because
>> of extioi limits, cpu internal interrupt such as timer/ipi can be
>> triggered on all cpus.
>>
>> Signed-off-by: Song Gao <gaosong@loongson.cn>
>> ---
>> hw/intc/loongarch_extioi.c | 4 ++--
>> hw/loongarch/virt.c | 21 ++++++++++++++-------
>> include/hw/intc/loongarch_extioi.h | 10 ++++++----
>> include/hw/loongarch/virt.h | 2 +-
>> 4 files changed, 23 insertions(+), 14 deletions(-)
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
>>
>> diff --git a/hw/intc/loongarch_extioi.c b/hw/intc/loongarch_extioi.c
>> index 4b8ec3f28a..0e7a3e32f3 100644
>> --- a/hw/intc/loongarch_extioi.c
>> +++ b/hw/intc/loongarch_extioi.c
>> @@ -254,7 +254,7 @@ static const VMStateDescription vmstate_loongarch_extioi = {
>> .minimum_version_id = 1,
>> .fields = (VMStateField[]) {
>> VMSTATE_UINT32_ARRAY(bounce, LoongArchExtIOI, EXTIOI_IRQS_GROUP_COUNT),
>> - VMSTATE_UINT32_2DARRAY(coreisr, LoongArchExtIOI, LOONGARCH_MAX_VCPUS,
>> + VMSTATE_UINT32_2DARRAY(coreisr, LoongArchExtIOI, EXTIOI_CPUS,
>> EXTIOI_IRQS_GROUP_COUNT),
>> VMSTATE_UINT32_ARRAY(nodetype, LoongArchExtIOI,
>> EXTIOI_IRQS_NODETYPE_COUNT / 2),
>> @@ -281,7 +281,7 @@ static void loongarch_extioi_instance_init(Object *obj)
>> qdev_init_gpio_in(DEVICE(obj), extioi_setirq, EXTIOI_IRQS);
>> - for (cpu = 0; cpu < LOONGARCH_MAX_VCPUS; cpu++) {
>> + for (cpu = 0; cpu < EXTIOI_CPUS; cpu++) {
>> memory_region_init_io(&s->extioi_iocsr_mem[cpu], OBJECT(s), &extioi_ops,
>> s, "extioi_iocsr", 0x900);
>> sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->extioi_iocsr_mem[cpu]);
>> diff --git a/hw/loongarch/virt.c b/hw/loongarch/virt.c
>> index c8a01b1fb6..28bb35d614 100644
>> --- a/hw/loongarch/virt.c
>> +++ b/hw/loongarch/virt.c
>> @@ -607,8 +607,13 @@ static void loongarch_irq_init(LoongArchMachineState *lams)
>> memory_region_add_subregion(&env->system_iocsr, MAIL_SEND_ADDR,
>> sysbus_mmio_get_region(SYS_BUS_DEVICE(ipi),
>> 1));
>> - /* extioi iocsr memory region */
>> - memory_region_add_subregion(&env->system_iocsr, APIC_BASE,
>> + /*
>> + * extioi iocsr memory region
>> + * only one extioi is added on loongarch virt machine
>> + * external device interrupt can only be routed to cpu 0-3
>> + */
>> + if (cpu < EXTIOI_CPUS)
>> + memory_region_add_subregion(&env->system_iocsr, APIC_BASE,
>> sysbus_mmio_get_region(SYS_BUS_DEVICE(extioi),
>> cpu));
>> }
>> @@ -618,10 +623,12 @@ static void loongarch_irq_init(LoongArchMachineState *lams)
>> * cpu_pin[9:2] <= intc_pin[7:0]
>> */
>> for (cpu = 0; cpu < ms->smp.cpus; cpu++) {
>> - cpudev = DEVICE(qemu_get_cpu(cpu));
>> - for (pin = 0; pin < LS3A_INTC_IP; pin++) {
>> - qdev_connect_gpio_out(extioi, (cpu * 8 + pin),
>> - qdev_get_gpio_in(cpudev, pin + 2));
>> + if (cpu < EXTIOI_CPUS) {
>> + cpudev = DEVICE(qemu_get_cpu(cpu));
>> + for (pin = 0; pin < LS3A_INTC_IP; pin++) {
>> + qdev_connect_gpio_out(extioi, (cpu * 8 + pin),
>> + qdev_get_gpio_in(cpudev, pin + 2));
>> + }
>> }
>> }
>> @@ -1026,7 +1033,7 @@ static void loongarch_class_init(ObjectClass *oc, void *data)
>> mc->default_ram_size = 1 * GiB;
>> mc->default_cpu_type = LOONGARCH_CPU_TYPE_NAME("la464");
>> mc->default_ram_id = "loongarch.ram";
>> - mc->max_cpus = LOONGARCH_MAX_VCPUS;
>> + mc->max_cpus = LOONGARCH_MAX_CPUS;
>> mc->is_default = 1;
>> mc->default_kernel_irqchip_split = false;
>> mc->block_default_type = IF_VIRTIO;
>> diff --git a/include/hw/intc/loongarch_extioi.h b/include/hw/intc/loongarch_extioi.h
>> index 15b8c999f6..fbdef9a7b3 100644
>> --- a/include/hw/intc/loongarch_extioi.h
>> +++ b/include/hw/intc/loongarch_extioi.h
>> @@ -14,6 +14,8 @@
>> #define LS3A_INTC_IP 8
>> #define EXTIOI_IRQS (256)
>> #define EXTIOI_IRQS_BITMAP_SIZE (256 / 8)
>> +/* irq from EXTIOI is routed to no more than 4 cpus */
>> +#define EXTIOI_CPUS (4)
>> /* map to ipnum per 32 irqs */
>> #define EXTIOI_IRQS_IPMAP_SIZE (256 / 32)
>> #define EXTIOI_IRQS_COREMAP_SIZE 256
>> @@ -46,17 +48,17 @@ struct LoongArchExtIOI {
>> uint32_t nodetype[EXTIOI_IRQS_NODETYPE_COUNT / 2];
>> uint32_t bounce[EXTIOI_IRQS_GROUP_COUNT];
>> uint32_t isr[EXTIOI_IRQS / 32];
>> - uint32_t coreisr[LOONGARCH_MAX_VCPUS][EXTIOI_IRQS_GROUP_COUNT];
>> + uint32_t coreisr[EXTIOI_CPUS][EXTIOI_IRQS_GROUP_COUNT];
>> uint32_t enable[EXTIOI_IRQS / 32];
>> uint32_t ipmap[EXTIOI_IRQS_IPMAP_SIZE / 4];
>> uint32_t coremap[EXTIOI_IRQS / 4];
>> uint32_t sw_pending[EXTIOI_IRQS / 32];
>> - DECLARE_BITMAP(sw_isr[LOONGARCH_MAX_VCPUS][LS3A_INTC_IP], EXTIOI_IRQS);
>> + DECLARE_BITMAP(sw_isr[EXTIOI_CPUS][LS3A_INTC_IP], EXTIOI_IRQS);
>> uint8_t sw_ipmap[EXTIOI_IRQS_IPMAP_SIZE];
>> uint8_t sw_coremap[EXTIOI_IRQS];
>> - qemu_irq parent_irq[LOONGARCH_MAX_VCPUS][LS3A_INTC_IP];
>> + qemu_irq parent_irq[EXTIOI_CPUS][LS3A_INTC_IP];
>> qemu_irq irq[EXTIOI_IRQS];
>> - MemoryRegion extioi_iocsr_mem[LOONGARCH_MAX_VCPUS];
>> + MemoryRegion extioi_iocsr_mem[EXTIOI_CPUS];
>> MemoryRegion extioi_system_mem;
>> };
>> #endif /* LOONGARCH_EXTIOI_H */
>> diff --git a/include/hw/loongarch/virt.h b/include/hw/loongarch/virt.h
>> index 54a9f595bb..f1659655c6 100644
>> --- a/include/hw/loongarch/virt.h
>> +++ b/include/hw/loongarch/virt.h
>> @@ -14,7 +14,7 @@
>> #include "hw/intc/loongarch_ipi.h"
>> #include "hw/block/flash.h"
>> -#define LOONGARCH_MAX_VCPUS 4
>> +#define LOONGARCH_MAX_CPUS 256
>> #define VIRT_ISA_IO_BASE 0x18000000UL
>> #define VIRT_ISA_IO_SIZE 0x0004000
>
next prev parent reply other threads:[~2023-05-10 10:12 UTC|newest]
Thread overview: 15+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-04-06 10:00 [PATCH 1/3] hw/loongarch/virt: Modify ipi as percpu device Song Gao
2023-04-06 10:00 ` [PATCH 2/3] hw/intc: Add NULL pointer check on LoongArch ipi device Song Gao
2023-04-26 1:37 ` Song Gao
2023-05-11 19:03 ` Philippe Mathieu-Daudé
2023-05-12 3:01 ` Song Gao
2023-05-12 3:45 ` Philippe Mathieu-Daudé
2023-05-12 6:29 ` Song Gao
2023-04-06 10:00 ` [PATCH 3/3] hw/loongarch/virt: Set max 256 cpus support on loongarch virt machine Song Gao
2023-04-26 1:37 ` Song Gao
2023-05-08 2:11 ` Song Gao
2023-05-10 10:12 ` Richard Henderson [this message]
2023-05-11 12:22 ` Song Gao
2023-05-11 19:07 ` Philippe Mathieu-Daudé
2023-04-26 1:38 ` [PATCH 1/3] hw/loongarch/virt: Modify ipi as percpu device Song Gao
2023-05-11 19:11 ` Philippe Mathieu-Daudé
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