From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1GfCFs-0007fq-7N for qemu-devel@nongnu.org; Wed, 01 Nov 2006 04:19:28 -0500 Received: from exim by lists.gnu.org with spam-scanned (Exim 4.43) id 1GfCFp-0007el-93 for qemu-devel@nongnu.org; Wed, 01 Nov 2006 04:19:27 -0500 Received: from [199.232.76.173] (helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1GfCFp-0007ei-1f for qemu-devel@nongnu.org; Wed, 01 Nov 2006 04:19:25 -0500 Received: from [64.233.162.193] (helo=nz-out-0102.google.com) by monty-python.gnu.org with esmtp (Exim 4.52) id 1GfCFn-00049j-7z for qemu-devel@nongnu.org; Wed, 01 Nov 2006 04:19:24 -0500 Received: by nz-out-0102.google.com with SMTP id 9so2481098nzo for ; Wed, 01 Nov 2006 01:19:14 -0800 (PST) Message-ID: Date: Wed, 1 Nov 2006 10:19:14 +0100 From: "Alessandro Corradi" Subject: Fwd: [Qemu-devel] Interrupt request info In-Reply-To: MIME-Version: 1.0 Content-Type: multipart/alternative; boundary="----=_Part_14751_16911292.1162372754222" References: <200610281501.41453.rob@landley.net> Reply-To: qemu-devel@nongnu.org List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel ------=_Part_14751_16911292.1162372754222 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Content-Disposition: inline ---------- Forwarded message ---------- From: Alessandro Corradi Date: 31-ott-2006 10.25 Subject: Re: [Qemu-devel] Interrupt request info To: Rob Landley I already read this, but give no usefull information... and I searched everywhere in the web... For example, I wrote a module of a simple memory without implementing IRQ... I think it is an error but it works fine... are IRQ raise in any case??? I look at other code source of implemented hw but for each device there is a differeny way to raise an interrupt (i see). Is there a standard way to do this? The following is an excerpt of my simple memory, please can you describe me fastly how can I manage this? Thank you struct scmemState { uint32_t data; uint32_t addr; uint32_t control; uint32_t comm; int irq; int irq_pending; }; scmemState *scmem_init(int base, int irq){ scmemState *s; s=qemu_mallocz(sizeof(scmemState)); s->irq = irq; s->data = 0; s->addr = 0; s->control = 0; ... } static void scmem_ioport_write(void *opaque, uint32_t addr, uint32_t val) { scmemState *s = opaque; addr &= 7; switch(addr) { case 0: cosim(1,DATA,val); s->data = val; #ifdef SCDEBUG printf("Writing at 0x738 (data reg) value= %d\n",val); #endif break; case 1: cosim(1,ADDR,val); s->addr = val; #ifdef SCDEBUG printf("Writing at 0x739 (addr reg) value= %d\n",val); #endif break; case 2: cosim(1,CONTROL,val); s->control = val; #ifdef SCDEBUG printf("Writing at 0x74a (control reg) value= %d\n",val); #endif break; case 3: if (val == 0x0003) { //SC socket connection restore scmem_restore(); } else { cosim(1,COMM,val); s->comm = val; #ifdef SCDEBUG printf("Writing at 0x74b (comm reg) value= %d\n",val); #endif } break; } } 2006/10/28, Rob Landley < rob@landley.net >: > > On Saturday 28 October 2006 5:36 am, Alessandro Corradi wrote: > > Hello, > > Can someone give me detailed information (or a link where it is > described) > > how qemu manage hw interrupts? > > I can't find any usefull info about it in QEMU doc. > > http://www.qemu.org/qemu-tech.html#SEC18 > > > ps: Obviously, if these information are already present I apologize me > in > > advance, I try to search but nothing was found :) > > The documentation is a bit sparse in places. > > Rob > -- > "Perfection is reached, not when there is no longer anything to add, but > when there is no longer anything to take away." - Antoine de Saint-Exupery > ------=_Part_14751_16911292.1162372754222 Content-Type: text/html; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit Content-Disposition: inline

---------- Forwarded message ----------
From: Alessandro Corradi <ale.corradi@gmail.com>
Date: 31-ott-2006 10.25
Subject: Re: [Qemu-devel] Interrupt request info
To: Rob Landley <rob@landley.net>

I already read this, but give no usefull information... and I searched everywhere in the web...
For example, I wrote a module of a simple memory without implementing IRQ... I think it is  an error but it works fine... are IRQ raise in any case???
I look at other code source of implemented hw but for each device there is a differeny way to raise an interrupt (i see).
Is there a standard way to do this?
The following is an excerpt of my simple memory, please can you describe me fastly how can I manage this?

Thank you


struct scmemState {
    uint32_t data;
    uint32_t addr;
    uint32_t control;
    uint32_t comm;

    int irq;
    int irq_pending;
};

scmemState *scmem_init(int base, int irq){
    scmemState *s;

    s=qemu_mallocz(sizeof(scmemState));
    s->irq = irq;
    s->data = 0;
    s->addr = 0;
    s->control = 0;
    ...
}
static void scmem_ioport_write(void *opaque, uint32_t addr, uint32_t val) {
    scmemState *s = opaque;
    addr &= 7;
    switch(addr) {
    case 0:
        cosim(1,DATA,val);
        s->data = val;
        #ifdef SCDEBUG
        printf("Writing at 0x738 (data reg) value= %d\n",val);
        #endif
        break;
    case 1:
        cosim(1,ADDR,val);
        s->addr = val;
        #ifdef SCDEBUG   
        printf("Writing at 0x739 (addr reg) value= %d\n",val);
        #endif
        break;
    case 2:
        cosim(1,CONTROL,val);
        s->control = val;
        #ifdef SCDEBUG   
        printf("Writing at 0x74a (control reg) value= %d\n",val);
        #endif
        break;
    case 3:
        if (val == 0x0003) { //SC socket connection restore
            scmem_restore();
        } else {
            cosim(1,COMM,val);
            s->comm = val;
            #ifdef SCDEBUG   
            printf("Writing at 0x74b (comm reg) value= %d\n",val);
            #endif
        }
        break;
    }
}


2006/10/28, Rob Landley < rob@landley.net >:
On Saturday 28 October 2006 5:36 am, Alessandro Corradi wrote:
> Hello,
> Can someone give me detailed information (or a link where it is described)
> how qemu manage hw interrupts?
> I can't find any usefull info about it in QEMU doc.

http://www.qemu.org/qemu-tech.html#SEC18

> ps: Obviously, if these information are already present I apologize me in
> advance, I try to search but nothing was found  :)

The documentation is a bit sparse in places.

Rob
--
"Perfection is reached, not when there is no longer anything to add, but
when there is no longer anything to take away." - Antoine de Saint-Exupery

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