From: "Philippe Mathieu-Daudé" <philmd@linaro.org>
To: Daniel Henrique Barboza <dbarboza@ventanamicro.com>,
Paolo Bonzini <pbonzini@redhat.com>,
qemu-devel@nongnu.org
Cc: alistair23@gmail.com, Alistair Francis <alistair.francis@wdc.com>
Subject: Re: [PATCH 08/27] target/riscv: store RISCVCPUDef struct directly in the class
Date: Thu, 24 Apr 2025 16:04:45 +0200 [thread overview]
Message-ID: <b92509a8-43e5-4515-b609-fcc17805c32f@linaro.org> (raw)
In-Reply-To: <8f3bae37-e1f3-4e55-9dc6-b7876992b47e@ventanamicro.com>
On 24/4/25 15:52, Daniel Henrique Barboza wrote:
> Hi,
>
> This patch breaks RISC-V KVM build in my env. The issues are down there:
>
> On 4/6/25 4:02 AM, Paolo Bonzini wrote:
>> Prepare for adding more fields to RISCVCPUDef and reading them in
>> riscv_cpu_init: instead of storing the misa_mxl_max field in
>> RISCVCPUClass, ensure that there's always a valid RISCVCPUDef struct
>> and go through it.
>>
>> Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
>> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
>> ---
>> target/riscv/cpu.h | 2 +-
>> hw/riscv/boot.c | 2 +-
>> target/riscv/cpu.c | 23 ++++++++++++++++++-----
>> target/riscv/gdbstub.c | 6 +++---
>> target/riscv/kvm/kvm-cpu.c | 21 +++++++++------------
>> target/riscv/machine.c | 2 +-
>> target/riscv/tcg/tcg-cpu.c | 10 +++++-----
>> target/riscv/translate.c | 2 +-
>> 8 files changed, 39 insertions(+), 29 deletions(-)
>> diff --git a/target/riscv/kvm/kvm-cpu.c b/target/riscv/kvm/kvm-cpu.c
>> index 0f4997a9186..d7e6970a670 100644
>> --- a/target/riscv/kvm/kvm-cpu.c
>> +++ b/target/riscv/kvm/kvm-cpu.c
>> @@ -1997,22 +1997,19 @@ static void kvm_cpu_accel_register_types(void)
>> }
>> type_init(kvm_cpu_accel_register_types);
>> -static void riscv_host_cpu_class_init(ObjectClass *c, void *data)
>> -{
>> - RISCVCPUClass *mcc = RISCV_CPU_CLASS(c);
>> -
>> -#if defined(TARGET_RISCV32)
>> - mcc->misa_mxl_max = MXL_RV32;
>> -#elif defined(TARGET_RISCV64)
>> - mcc->misa_mxl_max = MXL_RV64;
>> -#endif
>> -}
>> -
>> static const TypeInfo riscv_kvm_cpu_type_infos[] = {
>> {
>> .name = TYPE_RISCV_CPU_HOST,
>> .parent = TYPE_RISCV_CPU,
>> - .class_init = riscv_host_cpu_class_init,
>> +#if defined(TARGET_RISCV32)
>> + .class_data = &((const RISCVCPUDef) {
>> + .misa_mxl_max = MXL_RV32,
>> + },
>> +#elif defined(TARGET_RISCV64)
>> + .class_data = &((const RISCVCPUDef) {
>> + .misa_mxl_max = MXL_RV64,
>> + },
>> +#endif
>> }
>> };
>
>
> ../target/riscv/kvm/kvm-cpu.c:2013:5: error: expected expression before
> '}' token
> 2013 | }
> | ^
> ../target/riscv/kvm/kvm-cpu.c:2011:10: error: value computed is not used
> [-Werror=unused-value]
> 2011 | },
> | ^
> cc1: all warnings being treated as errors
> [11/13] Linking target qemu-nbd
>
>
> We're missing closing parenthesis after the "}".
>
> If we fix that we'll get another error:
>
> ../target/riscv/kvm/kvm-cpu.c:2009:23: error: initialization discards
> 'const' qualifier from pointer target type [-Werror=discarded-qualifiers]
> 2009 | .class_data = &((const RISCVCPUDef) {
> | ^
> cc1: all warnings being treated as errors
>
>
> Removing the 'const' qualifier fixes this other error.
Likely based on:
https://lore.kernel.org/qemu-devel/20250210133134.90879-1-philmd@linaro.org/
which was too late to get merged before soft-freeze, but
should get it soon.
next prev parent reply other threads:[~2025-04-24 14:05 UTC|newest]
Thread overview: 54+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-04-06 7:02 [PATCH 10.1 v3 00/27] target/riscv: SATP mode and CPU definition overhaul Paolo Bonzini
2025-04-06 7:02 ` [PATCH 01/27] hw/riscv: acpi: only create RHCT MMU entry for supported types Paolo Bonzini
2025-04-06 7:02 ` [PATCH 02/27] target/riscv: assert argument to set_satp_mode_max_supported is valid Paolo Bonzini
2025-04-06 7:02 ` [PATCH 03/27] target/riscv: cpu: store max SATP mode as a single integer Paolo Bonzini
2025-04-06 7:02 ` [PATCH 04/27] target/riscv: update max_satp_mode based on QOM properties Paolo Bonzini
2025-04-06 7:02 ` [PATCH 05/27] target/riscv: remove supported from RISCVSATPMap Paolo Bonzini
2025-04-06 7:02 ` [PATCH 06/27] target/riscv: move satp_mode.{map, init} out of CPUConfig Paolo Bonzini via
2025-04-06 7:02 ` [PATCH 07/27] target/riscv: introduce RISCVCPUDef Paolo Bonzini
2025-04-06 23:21 ` Alistair Francis
2025-04-06 7:02 ` [PATCH 08/27] target/riscv: store RISCVCPUDef struct directly in the class Paolo Bonzini
2025-04-24 13:52 ` Daniel Henrique Barboza
2025-04-24 14:04 ` Philippe Mathieu-Daudé [this message]
2025-04-24 14:21 ` Daniel Henrique Barboza
2025-04-06 7:02 ` [PATCH 09/27] target/riscv: merge riscv_cpu_class_init with the class_base function Paolo Bonzini
2025-04-06 7:02 ` [PATCH 10/27] target/riscv: move RISCVCPUConfig fields to a header file Paolo Bonzini
2025-04-06 7:02 ` [PATCH 11/27] target/riscv: include default value in cpu_cfg_fields.h.inc Paolo Bonzini
2025-04-09 4:53 ` Alistair Francis
2025-04-06 7:02 ` [PATCH 12/27] target/riscv: do not make RISCVCPUConfig fields conditional Paolo Bonzini
2025-04-09 5:12 ` Alistair Francis
2025-04-06 7:02 ` [PATCH 13/27] target/riscv: add more RISCVCPUDef fields Paolo Bonzini
2025-04-22 4:47 ` Alistair Francis
2025-04-06 7:02 ` [PATCH 14/27] target/riscv: convert abstract CPU classes to RISCVCPUDef Paolo Bonzini
2025-04-24 0:50 ` Alistair Francis
2025-04-06 7:02 ` [PATCH 15/27] target/riscv: convert profile CPU models " Paolo Bonzini
2025-04-24 0:11 ` Alistair Francis
2025-04-06 7:02 ` [PATCH 16/27] target/riscv: convert bare " Paolo Bonzini
2025-04-24 0:12 ` Alistair Francis
2025-04-06 7:02 ` [PATCH 17/27] target/riscv: convert dynamic " Paolo Bonzini
2025-04-24 0:15 ` Alistair Francis
2025-04-06 7:02 ` [PATCH 18/27] target/riscv: convert SiFive E " Paolo Bonzini
2025-04-24 0:22 ` Alistair Francis
2025-04-06 7:02 ` [PATCH 19/27] target/riscv: convert ibex " Paolo Bonzini
2025-04-24 0:23 ` Alistair Francis
2025-04-06 7:02 ` [PATCH 20/27] target/riscv: convert SiFive U " Paolo Bonzini
2025-04-24 0:25 ` Alistair Francis
2025-04-06 7:02 ` [PATCH 21/27] target/riscv: th: make CSR insertion test a bit more intuitive Paolo Bonzini
2025-04-24 0:32 ` Alistair Francis
2025-04-06 7:02 ` [PATCH 22/27] target/riscv: generalize custom CSR functionality Paolo Bonzini
2025-04-24 0:36 ` Alistair Francis
2025-04-06 7:02 ` [PATCH 23/27] target/riscv: convert TT C906 to RISCVCPUDef Paolo Bonzini
2025-04-24 0:37 ` Alistair Francis
2025-04-06 7:02 ` [PATCH 24/27] target/riscv: convert TT Ascalon " Paolo Bonzini
2025-04-24 0:38 ` Alistair Francis
2025-04-06 7:02 ` [PATCH 25/27] target/riscv: convert Ventana V1 " Paolo Bonzini
2025-04-24 0:45 ` Alistair Francis
2025-04-06 7:02 ` [PATCH 26/27] target/riscv: convert Xiangshan Nanhu " Paolo Bonzini
2025-04-24 0:47 ` Alistair Francis
2025-04-06 7:02 ` [PATCH 27/27] target/riscv: remove .instance_post_init Paolo Bonzini
2025-04-24 0:48 ` Alistair Francis
2025-04-24 1:26 ` [PATCH 10.1 v3 00/27] target/riscv: SATP mode and CPU definition overhaul Alistair Francis
2025-04-24 14:39 ` Paolo Bonzini
2025-04-25 10:55 ` Paolo Bonzini
2025-04-25 11:02 ` Philippe Mathieu-Daudé
2025-04-25 11:03 ` Paolo Bonzini
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