Re: [RFC PATCH v3 08/21] target/arm: Handle IS/FS in ISR_EL1 for NMI

[Richard Henderson <richard.henderson@linaro.org>]

On 2/23/24 00:32, Jinjie Ruan via wrote:
> Add IS and FS bit in ISR_EL1 and handle the read. With CPU_INTERRUPT_NMI, both
> CPSR_I and ISR_IS must be set.
> 
> Signed-off-by: Jinjie Ruan <ruanjinjie@huawei.com>
> --
> v3:
> - CPU_INTERRUPT_NMI do not set FIQ, so remove it.
> - With CPU_INTERRUPT_NMI, both CPSR_I and ISR_IS must be set.
> ---
>   target/arm/cpu.h    | 2 ++
>   target/arm/helper.c | 5 +++++
>   2 files changed, 7 insertions(+)
> 
> diff --git a/target/arm/cpu.h b/target/arm/cpu.h
> index b23be7fc24..ae9a75d717 100644
> --- a/target/arm/cpu.h
> +++ b/target/arm/cpu.h
> @@ -1476,6 +1476,8 @@ FIELD(CPTR_EL3, TCPAC, 31, 1)
>   #define CPSR_N (1U << 31)
>   #define CPSR_NZCV (CPSR_N | CPSR_Z | CPSR_C | CPSR_V)
>   #define CPSR_AIF (CPSR_A | CPSR_I | CPSR_F)
> +#define ISR_FS (1U << 9)
> +#define ISR_IS (1U << 10)
>   
>   #define CPSR_IT (CPSR_IT_0_1 | CPSR_IT_2_7)
>   #define CACHED_CPSR_BITS (CPSR_T | CPSR_AIF | CPSR_GE | CPSR_IT | CPSR_Q \
> diff --git a/target/arm/helper.c b/target/arm/helper.c
> index 2f54413b01..eb97ce0356 100644
> --- a/target/arm/helper.c
> +++ b/target/arm/helper.c
> @@ -2022,6 +2022,11 @@ static uint64_t isr_read(CPUARMState *env, const ARMCPRegInfo *ri)
>           if (cs->interrupt_request & CPU_INTERRUPT_HARD) {
>               ret |= CPSR_I;
>           }
> +
> +        if (cs->interrupt_request & CPU_INTERRUPT_NMI) {
> +            ret |= ISR_IS;
> +            ret |= CPSR_I;
> +        }
>       }

Need to handle CPU_INTERRUPT_VNMI (which can be raised from the GIC).

Need to handle HCRX_EL2.VFNMI with CPU_INTERRUPT_VFIQ (which cannot be raised from the 
GIC, so we can determine VFIQ superpriority based solely on the cpu state).


r~