From: "Philippe Mathieu-Daudé" <philmd@linaro.org>
To: Aleksei Filippov <alexei.filippov@syntacore.com>,
Richard Henderson <richard.henderson@linaro.org>,
palmer@dabbelt.com
Cc: alistair.francis@wdc.com, bmeng.cn@gmail.com,
dbarboza@ventanamicro.com, zhiwei_liu@linux.alibaba.com,
liwei1518@gmail.com, qemu-devel@nongnu.org,
qemu-riscv@nongnu.org
Subject: Re: [PATCH v2] target/riscv: Add support for machine specific pmu's events
Date: Mon, 8 Jul 2024 15:42:36 +0200 [thread overview]
Message-ID: <b94c987e-835a-490f-a4d4-72f87db7f7b1@linaro.org> (raw)
In-Reply-To: <a019a09d-9549-4fa9-8b30-befb4df96fc0@syntacore.com>
Hi Aleksei,
On 8/7/24 11:46, Aleksei Filippov wrote:
> On 25.06.2024 21:18, Richard Henderson wrote:
>> On 6/25/24 07:46, Alexei Filippov wrote:
>>> Was added call backs for machine specific pmu events.
>>> Simplify monitor functions by adding new hash table, which going to map
>>> counter number and event index.
>>> Was added read/write callbacks which going to simplify support for
>>> events,
>>> which expected to have different behavior.
>>>
>>> Signed-off-by: Alexei Filippov <alexei.filippov@syntacore.com>
>>> ---
>>> Changes since v2:
>>> -rebased to latest master
>>> target/riscv/cpu.h | 9 +++
>>> target/riscv/csr.c | 43 +++++++++-----
>>> target/riscv/pmu.c | 139 ++++++++++++++++++++++-----------------------
>>> target/riscv/pmu.h | 11 ++--
>>> 4 files changed, 115 insertions(+), 87 deletions(-)
>>>
>>> diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
>>> index 6fe0d712b4..fbf82b050b 100644
>>> --- a/target/riscv/cpu.h
>>> +++ b/target/riscv/cpu.h
>>> @@ -374,6 +374,13 @@ struct CPUArchState {
>>> uint64_t (*rdtime_fn)(void *);
>>> void *rdtime_fn_arg;
>>> + /*machine specific pmu callback */
>>> + void (*pmu_ctr_write)(PMUCTRState *counter, uint32_t event_idx,
>>> + target_ulong val, bool high_half);
>>> + target_ulong (*pmu_ctr_read)(PMUCTRState *counter, uint32_t
>>> event_idx,
>>> + bool high_half);
>>> + bool (*pmu_vendor_support)(uint32_t event_idx);
>>
>> Do these really belong in CPUArchState, rather than RISCVCPUClass?
>>
>> Surely there's more to this series, since these fields are never set...
>>
>>
>> r~
>
> Initially this callbacks was added to CPUArchState just to be along with
> similar implementation with rdtime_fn*.
>
> Yes, you're right, there are more series to this, but, it can't be
> separated from syntacore specific parts, which is unfortunately not
> ready yet to be published. So, I can prepare second patch to implement
> PMU subsystem for virt device. What do you think about it? (I'll send it
> in the few days).
How can we test your patch meanwhile?
Thanks,
Phil.
next prev parent reply other threads:[~2024-07-08 13:43 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-06-25 14:46 [PATCH v2] target/riscv: Add support for machine specific pmu's events Alexei Filippov
2024-06-25 18:18 ` Richard Henderson
2024-07-08 9:46 ` Aleksei Filippov
2024-07-08 13:42 ` Philippe Mathieu-Daudé [this message]
2024-09-11 8:50 ` Aleksei Filippov
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