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Mon, 08 Jul 2024 06:42:38 -0700 (PDT) Message-ID: Date: Mon, 8 Jul 2024 15:42:36 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2] target/riscv: Add support for machine specific pmu's events To: Aleksei Filippov , Richard Henderson , palmer@dabbelt.com Cc: alistair.francis@wdc.com, bmeng.cn@gmail.com, dbarboza@ventanamicro.com, zhiwei_liu@linux.alibaba.com, liwei1518@gmail.com, qemu-devel@nongnu.org, qemu-riscv@nongnu.org References: <20240625144643.34733-1-alexei.filippov@syntacore.com> <2cb94b34-1a5f-4dc9-bec4-78c7008cd79d@linaro.org> Content-Language: en-US From: =?UTF-8?Q?Philippe_Mathieu-Daud=C3=A9?= In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::329; envelope-from=philmd@linaro.org; helo=mail-wm1-x329.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Hi Aleksei, On 8/7/24 11:46, Aleksei Filippov wrote: > On 25.06.2024 21:18, Richard Henderson wrote: >> On 6/25/24 07:46, Alexei Filippov wrote: >>> Was added call backs for machine specific pmu events. >>> Simplify monitor functions by adding new hash table, which going to map >>> counter number and event index. >>> Was added read/write callbacks which going to simplify support for >>> events, >>> which expected to have different behavior. >>> >>> Signed-off-by: Alexei Filippov >>> --- >>> Changes since v2: >>>         -rebased to latest master >>>   target/riscv/cpu.h |   9 +++ >>>   target/riscv/csr.c |  43 +++++++++----- >>>   target/riscv/pmu.c | 139 ++++++++++++++++++++++----------------------- >>>   target/riscv/pmu.h |  11 ++-- >>>   4 files changed, 115 insertions(+), 87 deletions(-) >>> >>> diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h >>> index 6fe0d712b4..fbf82b050b 100644 >>> --- a/target/riscv/cpu.h >>> +++ b/target/riscv/cpu.h >>> @@ -374,6 +374,13 @@ struct CPUArchState { >>>       uint64_t (*rdtime_fn)(void *); >>>       void *rdtime_fn_arg; >>> +    /*machine specific pmu callback */ >>> +    void (*pmu_ctr_write)(PMUCTRState *counter, uint32_t event_idx, >>> +                          target_ulong val, bool high_half); >>> +    target_ulong (*pmu_ctr_read)(PMUCTRState *counter, uint32_t >>> event_idx, >>> +                                 bool high_half); >>> +    bool (*pmu_vendor_support)(uint32_t event_idx); >> >> Do these really belong in CPUArchState, rather than RISCVCPUClass? >> >> Surely there's more to this series, since these fields are never set... >> >> >> r~ > > Initially this callbacks was added to CPUArchState just to be along with > similar implementation with rdtime_fn*. > > Yes, you're right, there are more series to this, but, it can't be > separated from syntacore specific parts, which is unfortunately not > ready yet to be published. So, I can prepare second patch to implement > PMU subsystem for virt device. What do you think about it? (I'll send it > in the few days). How can we test your patch meanwhile? Thanks, Phil.