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([2001:8004:5170:1fd8:ef9d:e346:b99e:7072]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-2d8c399f7c9sm1585028a91.21.2024.09.01.17.12.55 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Sun, 01 Sep 2024 17:12:59 -0700 (PDT) Message-ID: Date: Mon, 2 Sep 2024 10:12:51 +1000 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2 02/14] util: Add RISC-V vector extension probe in cpuinfo To: LIU Zhiwei , qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, palmer@dabbelt.com, alistair.francis@wdc.com, dbarboza@ventanamicro.com, liwei1518@gmail.com, bmeng.cn@gmail.com, TANG Tiancheng References: <20240830061607.1940-1-zhiwei_liu@linux.alibaba.com> <20240830061607.1940-3-zhiwei_liu@linux.alibaba.com> Content-Language: en-US From: Richard Henderson In-Reply-To: <20240830061607.1940-3-zhiwei_liu@linux.alibaba.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=2607:f8b0:4864:20::1030; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1030.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On 8/30/24 16:15, LIU Zhiwei wrote: > +extern unsigned riscv_vlen; Do you really want to store vlen and not vlenb? It seems that would simplify some of your computation in the tcg backend. > @@ -49,6 +50,9 @@ unsigned __attribute__((constructor)) cpuinfo_init(void) > #endif > #if defined(__riscv_arch_test) && defined(__riscv_zicond) > info |= CPUINFO_ZICOND; > +#endif > +#if defined(__riscv_arch_test) && defined(__riscv_zve64x) > + info |= CPUINFO_ZVE64X; > #endif > left &= ~info; > > @@ -64,7 +68,8 @@ unsigned __attribute__((constructor)) cpuinfo_init(void) > && pair.key >= 0) { > info |= pair.value & RISCV_HWPROBE_EXT_ZBA ? CPUINFO_ZBA : 0; > info |= pair.value & RISCV_HWPROBE_EXT_ZBB ? CPUINFO_ZBB : 0; > - left &= ~(CPUINFO_ZBA | CPUINFO_ZBB); > + info |= pair.value & RISCV_HWPROBE_IMA_V ? CPUINFO_ZVE64X : 0; > + left &= ~(CPUINFO_ZBA | CPUINFO_ZBB | CPUINFO_ZVE64X); > #ifdef RISCV_HWPROBE_EXT_ZICOND > info |= pair.value & RISCV_HWPROBE_EXT_ZICOND ? CPUINFO_ZICOND : 0; > left &= ~CPUINFO_ZICOND; > @@ -112,6 +117,23 @@ unsigned __attribute__((constructor)) cpuinfo_init(void) > assert(left == 0); > } > > + if (info & CPUINFO_ZVE64X) { > + /* > + * Get vlen for Vector. > + * VLMAX = LMUL * VLEN / SEW. > + * The "vsetvli rd, x0, e64" means "LMUL = 1, SEW = 64, rd = VLMAX", > + * so "vlen = VLMAX * 64". > + */ > + unsigned long vlmax = 0; > + asm("vsetvli %0, x0, e64" : "=r"(vlmax)); This doesn't compile, surely. s/x0/zero/ is surely the minimum change, but this still won't work unless V is enabled at compile-time. You need to use the .insn form, like we do for the Zba probe above: .insn i 0x57, 7, %0, zero, 3 << 3 I have verified that RISCV_HWPROBE_IMA_V went into the linux kernel at the same time as vector support, so this probing is complete and sufficient. r~