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Fri, 29 Sep 2023 19:13:42 -0700 (PDT) Message-ID: Date: Fri, 29 Sep 2023 19:13:40 -0700 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.15.1 Subject: Re: [PATCH 0/7] tcg/loongarch64: Improvements for 128-bit load/store From: Richard Henderson To: qemu-devel@nongnu.org Cc: git@xen0n.name, c@jia.je, gaosong@loongson.cn, yangxiaojuan@loongson.cn References: <20230916220151.526140-1-richard.henderson@linaro.org> Content-Language: en-US In-Reply-To: <20230916220151.526140-1-richard.henderson@linaro.org> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=2607:f8b0:4864:20::533; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x533.google.com X-Spam_score_int: -53 X-Spam_score: -5.4 X-Spam_bar: ----- X-Spam_report: (-5.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, NICE_REPLY_A=-3.295, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Ping. r~ On 9/16/23 15:01, Richard Henderson wrote: > For tcg generated code, use new registers with load so that we never > overlap the input address, so that we can simplify address build for > 64-bit user-only. > > For tcg out-of-line code, implement the host/ headers to for atomic 128-bit > load and store, reducing the cases for which we must raise EXCP_ATOMIC. > > > r~ > > Based-on: 20230916171223.521545-1-richard.henderson@linaro.org > ("[PULL v2 00/39] tcg patch queue") > > Richard Henderson (7): > tcg: Add C_N2_I1 > tcg/loongarch64: Use C_N2_I1 for INDEX_op_qemu_ld_a*_i128 > util: Add cpuinfo for loongarch64 > tcg/loongarch64: Use cpuinfo.h > host/include/loongarch64: Add atomic16 load and store > accel/tcg: Remove redundant case in store_atom_16 > accel/tcg: Fix condition for store_atom_insert_al16 > > .../include/loongarch64/host/atomic128-ldst.h | 52 +++++++++++++++++++ > host/include/loongarch64/host/cpuinfo.h | 21 ++++++++ > .../loongarch64/host/load-extract-al16-al8.h | 39 ++++++++++++++ > .../loongarch64/host/store-insert-al16.h | 12 +++++ > tcg/loongarch64/tcg-target-con-set.h | 2 +- > tcg/loongarch64/tcg-target.h | 8 +-- > accel/tcg/cputlb.c | 2 +- > tcg/tcg.c | 5 ++ > util/cpuinfo-loongarch.c | 35 +++++++++++++ > accel/tcg/ldst_atomicity.c.inc | 14 ++--- > tcg/loongarch64/tcg-target.c.inc | 25 +++++---- > util/meson.build | 2 + > 12 files changed, 189 insertions(+), 28 deletions(-) > create mode 100644 host/include/loongarch64/host/atomic128-ldst.h > create mode 100644 host/include/loongarch64/host/cpuinfo.h > create mode 100644 host/include/loongarch64/host/load-extract-al16-al8.h > create mode 100644 host/include/loongarch64/host/store-insert-al16.h > create mode 100644 util/cpuinfo-loongarch.c >