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[200.207.147.180]) by smtp.gmail.com with ESMTPSA id t6-20020a056870f20600b0010d5d5c3fc3sm6928337oao.8.2022.09.06.13.08.01 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 06 Sep 2022 13:08:04 -0700 (PDT) Message-ID: Date: Tue, 6 Sep 2022 17:07:59 -0300 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.2.0 Subject: Re: [PATCH v2 0/8] Multiple ppc instructions fixes Content-Language: en-US To: =?UTF-8?Q?V=c3=adctor_Colombo?= , qemu-devel@nongnu.org, qemu-ppc@nongnu.org Cc: clg@kaod.org, david@gibson.dropbear.id.au, groug@kaod.org, richard.henderson@linaro.org, matheus.ferst@eldorado.org.br, lucas.araujo@eldorado.org.br, leandro.lupori@eldorado.org.br, lucas.coutinho@eldorado.org.br References: <20220906125523.38765-1-victor.colombo@eldorado.org.br> From: Daniel Henrique Barboza In-Reply-To: <20220906125523.38765-1-victor.colombo@eldorado.org.br> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::331; envelope-from=danielhb413@gmail.com; helo=mail-ot1-x331.google.com X-Spam_score_int: -35 X-Spam_score: -3.6 X-Spam_bar: --- X-Spam_report: (-3.6 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, NICE_REPLY_A=-1.752, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Queued in gitlab.com/danielhb/qemu/tree/ppc-next. Thanks, Daniel On 9/6/22 09:55, Víctor Colombo wrote: > This patch set fixes multiple instructions for PPC targets that were > producing incorrect results, or setting the wrong bits in FPSCR. > > Patch 1 is just a style fix, trivial. > Patch 8 adds helper_reset_fpstatus() calls to instructions > that have an issue where the exception flags are being kept from > the previous instruction, causing incorrect bits to be set, > specially the non-sticky FI bit. > Other patches fixes other specific situations. > > v1->v2: > - Squash patches 8 through 19 and write a better commit message to it. > - Dropped Daniel's R-b in the squashed patches, as the squash merged > both reviewed and non-reviewed patches. Now require a new, single > R-b. > > Víctor Colombo (8): > target/ppc: Remove extra space from s128 field in ppc_vsr_t > target/ppc: Remove unused xer_* macros > target/ppc: Zero second doubleword in DFP instructions > target/ppc: Set result to QNaN for DENBCD when VXCVI occurs > target/ppc: Zero second doubleword for VSX madd instructions > target/ppc: Set OV32 when OV is set > target/ppc: Zero second doubleword of VSR registers for FPR insns > target/ppc: Clear fpstatus flags on helpers missing it > > target/ppc/cpu.h | 6 +----- > target/ppc/dfp_helper.c | 31 ++++++++++++++++++++++++++++--- > target/ppc/fpu_helper.c | 39 +++++++++++++++++++++++++++------------ > target/ppc/int_helper.c | 4 ++-- > target/ppc/translate.c | 8 ++++++++ > 5 files changed, 66 insertions(+), 22 deletions(-) >